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/linux-6.15/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml130 When the DRAM type is DDR3, this parameter defines the ODT disable
132 the ODT on the DRAM side and controller side are both disabled.
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
180 ODT on the DRAM side and controller side are both disabled.
186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
227 the ODT on the DRAM side and controller side are both disabled.
233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
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H A Dsamsung,exynos5422-dmc.yaml17 DRAM memory chips are connected. The driver is to monitor the controller in
55 phandle of the connected DRAM memory device. For more information please
/linux-6.15/Documentation/hid/
H A Damd-sfh-hid.rst60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On
72 2. Data transfer via DRAM.
77 the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client
78 layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver
79 shall allocate minimum of 32 bytes DRAM space.
103 | | | Allocate the DRAM | Enable |
136 | | | Read the DRAM data for| | |
/linux-6.15/Documentation/devicetree/bindings/interconnect/
H A Dmediatek,mt8183-emi.yaml22 | |->| DRAM | ---- | ----
23 |DRAM |->|scheduler|----- |GPU | |--- |DISP|
29 | change DRAM freq |--- |VENC|
/linux-6.15/drivers/memory/tegra/
H A DKconfig22 Tegra20 chips. The EMC controls the external DRAM on the board.
34 Tegra30 chips. The EMC controls the external DRAM on the board.
46 Tegra124 chips. The EMC controls the external DRAM on the board.
60 Tegra210 chips. The EMC controls the external DRAM on the board.
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll5-clk.yaml7 title: Allwinner A10 DRAM PLL
19 The first output is the DRAM clock output, the second is meant
/linux-6.15/sound/isa/gus/
H A Dgus_dram.c28 outsb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_poke()
64 insb(GUSP(gus, DRAM), buffer, size1); in snd_gus_dram_peek()
/linux-6.15/drivers/memory/samsung/
H A DKconfig19 Frequency Scaling in DMC and DRAM. It also supports changing timings
20 of DRAM running with different frequency. The timings are calculated
/linux-6.15/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra210-bpmp.txt6 (suspend to ram), and also offloading DRAM memory clock scaling on
23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
/linux-6.15/Documentation/devicetree/bindings/arm/sunxi/
H A Dallwinner,sun4i-a10-mbus.yaml51 - description: DRAM controller/PHY registers
63 - description: DRAM controller/PHY module clock
64 - description: Register bus clock, shared by MBUS and DRAM
/linux-6.15/arch/arm/configs/
H A Ddram_0xc0000000.config1 # Help: DRAM base at 0xc0000000
H A Ddram_0xd0000000.config1 # Help: DRAM base at 0xd0000000
H A Ddram_0x00000000.config1 # Help: DRAM base at 0x00000000
/linux-6.15/Documentation/driver-api/
H A Dedac.rst18 The individual DRAM chips on a memory stick. These devices commonly
69 This is the name of the DRAM signal used to select the DRAM ranks to be
112 communication lanes. It uses vertically stacked memory chips (DRAM dies)
202 of 4096-bits of DRAM data bus.
204 While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC
205 channel is interfacing 2GB of DRAM (represented as rank).
/linux-6.15/Documentation/edac/
H A Dmemory_repair.rst30 in a DRAM device.
32 For example, a CXL memory device with DRAM components that support PPR
33 features implements maintenance operations. DRAM components support those
95 media or DRAM trace event to userspace, and userspace tools (e.g.
H A Dscrub.rst19 Increasing DRAM size and cost have made memory subsystem reliability an
47 1. Background (patrol) scrubbing while the DRAM is otherwise idle.
131 allowing DRAM to internally read, correct single-bit errors, and write back
132 corrected data bits to the DRAM array while providing transparency to error
242 | reporting | Exception |media/DRAM |media/DRAM | notify and|
/linux-6.15/Documentation/admin-guide/perf/
H A Dmeson-ddr-pmu.rst7 The Amlogic Meson G12 SoC contains a bandwidth monitor inside DRAM controller.
9 DRAM. The channel can count up to 3 AXI port simultaneously. It can be helpful
/linux-6.15/arch/arm/
H A DKconfig-nommu14 hex '(S)DRAM Base Address' if SET_MEM_PARAM
18 hex '(S)DRAM SIZE' if SET_MEM_PARAM
/linux-6.15/Documentation/translations/zh_CN/mm/damon/
H A Dindex.rst19 - *准确度* （监测输出对DRAM级别的内存管理足够有用；但可能不适合CPU Cache级别），
/linux-6.15/Documentation/devicetree/bindings/media/
H A Dallwinner,sun4i-a10-csi.yaml39 - description: The CSI DRAM clock
44 - description: The CSI DRAM clock
/linux-6.15/Documentation/hwmon/
H A Dasus_wmi_sensors.rst37 * DRAM Voltage,
48 * DRAM Voltage,
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-edac-memory-repair15 replacing it with a spare row in a DRAM device. For example, a
16 CXL memory device with DRAM components that support PPR features may
17 implement PPR maintenance operations. DRAM components may support
142 related error records and trace events, for eg. CXL DRAM
160 in trace events, such as CXL DRAM and CXL general media
/linux-6.15/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-board-base.dtsi22 &memory { /* Default DRAM banks */
/linux-6.15/arch/arm/mach-lpc32xx/
H A Dsuspend.S51 @ This guarantees a small windows where DRAM isn't busy
/linux-6.15/drivers/ras/amd/atl/
H A DKconfig21 Enable this option if using DRAM ECC on Zen-based systems

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