Home
last modified time | relevance | path

Searched refs:DP_TP_CTL (Results 1 – 5 of 5) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c921 intel_de_write(display, DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
982 intel_de_rmw(display, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); in hsw_fdi_link_train()
983 intel_de_posting_read(display, DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
995 intel_de_write(display, DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
H A Dintel_ddi.c2264 return DP_TP_CTL(encoder->port); in dp_tp_ctl_reg()
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c529 MMIO_D(DP_TP_CTL(PORT_A)); in iterate_generic_mmio()
530 MMIO_D(DP_TP_CTL(PORT_B)); in iterate_generic_mmio()
531 MMIO_D(DP_TP_CTL(PORT_C)); in iterate_generic_mmio()
532 MMIO_D(DP_TP_CTL(PORT_D)); in iterate_generic_mmio()
533 MMIO_D(DP_TP_CTL(PORT_E)); in iterate_generic_mmio()
H A Di915_reg.h3548 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) macro
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c833 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); in fdi_auto_training_started()
953 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
2370 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2371 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2372 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2373 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2374 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()