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Searched refs:DPU_REG_WRITE (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_util.c173 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3_lut()
225 DPU_REG_WRITE(c, in _dpu_hw_setup_scaler3lite_lut()
395 DPU_REG_WRITE(c, csc_reg_off, val); in dpu_hw_csc_setup()
398 DPU_REG_WRITE(c, csc_reg_off + 0x4, val); in dpu_hw_csc_setup()
401 DPU_REG_WRITE(c, csc_reg_off + 0x8, val); in dpu_hw_csc_setup()
404 DPU_REG_WRITE(c, csc_reg_off + 0xc, val); in dpu_hw_csc_setup()
406 DPU_REG_WRITE(c, csc_reg_off + 0x10, val); in dpu_hw_csc_setup()
410 DPU_REG_WRITE(c, csc_reg_off + 0x14, val); in dpu_hw_csc_setup()
412 DPU_REG_WRITE(c, csc_reg_off + 0x18, val); in dpu_hw_csc_setup()
474 DPU_REG_WRITE(c, offset + QOS_QOS_CTRL, in _dpu_hw_setup_qos_lut()
[all …]
H A Ddpu_hw_dsc_1_2.c81 DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CFG, 0); in dpu_hw_dsc_disable_1_2()
83 DPU_REG_WRITE(hw, sblk->enc.base + ENC_DF_CTRL, 0); in dpu_hw_dsc_disable_1_2()
84 DPU_REG_WRITE(hw, sblk->enc.base + DSC_MAIN_CONF, 0); in dpu_hw_dsc_disable_1_2()
118 DPU_REG_WRITE(hw, DSC_CMN_MAIN_CNF, data); in dpu_hw_dsc_config_1_2()
167 DPU_REG_WRITE(hw, sblk->enc.base + DSC_MISC_SIZE, in dpu_hw_dsc_config_1_2()
175 DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_SCALE, in dpu_hw_dsc_config_1_2()
238 DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CFG, data); in dpu_hw_dsc_config_1_2()
288 DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_0, in dpu_hw_dsc_config_thresh_1_2()
294 DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MAX_QP_0, in dpu_hw_dsc_config_thresh_1_2()
307 DPU_REG_WRITE(hw, sblk->enc.base + DSC_RC_MIN_QP_1, in dpu_hw_dsc_config_thresh_1_2()
[all …]
H A Ddpu_hw_dsc.c42 DPU_REG_WRITE(c, DSC_COMMON_MODE, 0); in dpu_hw_dsc_disable()
57 DPU_REG_WRITE(c, DSC_COMMON_MODE, mode); in dpu_hw_dsc_config()
74 DPU_REG_WRITE(c, DSC_ENC, data); in dpu_hw_dsc_config()
78 DPU_REG_WRITE(c, DSC_PICTURE, data); in dpu_hw_dsc_config()
82 DPU_REG_WRITE(c, DSC_SLICE, data); in dpu_hw_dsc_config()
85 DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data); in dpu_hw_dsc_config()
89 DPU_REG_WRITE(c, DSC_DELAY, data); in dpu_hw_dsc_config()
105 DPU_REG_WRITE(c, DSC_BPG_OFFSET, data); in dpu_hw_dsc_config()
109 DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); in dpu_hw_dsc_config()
115 DPU_REG_WRITE(c, DSC_FLATNESS, data); in dpu_hw_dsc_config()
[all …]
H A Ddpu_hw_intf.c224 DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl); in dpu_hw_intf_setup_timing_engine()
226 DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0, in dpu_hw_intf_setup_timing_engine()
239 DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); in dpu_hw_intf_setup_timing_engine()
250 DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); in dpu_hw_intf_setup_timing_engine()
280 DPU_REG_WRITE(c, INTF_PROG_FETCH_START, in dpu_hw_intf_setup_prg_fetch()
286 DPU_REG_WRITE(c, INTF_CONFIG, fetch_enable); in dpu_hw_intf_setup_prg_fetch()
304 DPU_REG_WRITE(c, INTF_MUX, mux_cfg); in dpu_hw_intf_bind_pingpong_blk()
373 DPU_REG_WRITE(c, INTF_TEAR_SYNC_THRESH, in dpu_hw_intf_enable_te()
376 DPU_REG_WRITE(c, INTF_TEAR_SYNC_WRCOUNT, in dpu_hw_intf_enable_te()
379 DPU_REG_WRITE(c, INTF_TEAR_TEAR_CHECK_EN, 1); in dpu_hw_intf_enable_te()
[all …]
H A Ddpu_hw_dspp.c47 DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); in dpu_setup_dspp_pcc()
51 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r); in dpu_setup_dspp_pcc()
52 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g); in dpu_setup_dspp_pcc()
53 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_B_OFF, cfg->r.b); in dpu_setup_dspp_pcc()
55 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_R_OFF, cfg->g.r); in dpu_setup_dspp_pcc()
56 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_G_OFF, cfg->g.g); in dpu_setup_dspp_pcc()
57 DPU_REG_WRITE(&ctx->hw, base + PCC_GREEN_B_OFF, cfg->g.b); in dpu_setup_dspp_pcc()
59 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_R_OFF, cfg->b.r); in dpu_setup_dspp_pcc()
60 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_G_OFF, cfg->b.g); in dpu_setup_dspp_pcc()
61 DPU_REG_WRITE(&ctx->hw, base + PCC_BLUE_B_OFF, cfg->b.b); in dpu_setup_dspp_pcc()
[all …]
H A Ddpu_hw_ctl.c94 DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1); in dpu_hw_ctl_trigger_start()
146 DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
149 DPU_REG_WRITE(&ctx->hw, CTL_WB_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
152 DPU_REG_WRITE(&ctx->hw, CTL_CWB_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
158 DPU_REG_WRITE(&ctx->hw, in dpu_hw_ctl_trigger_flush_v1()
168 DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
172 DPU_REG_WRITE(&ctx->hw, CTL_CDM_FLUSH, in dpu_hw_ctl_trigger_flush_v1()
426 DPU_REG_WRITE(c, CTL_SW_RESET, 0x1); in dpu_hw_ctl_reset_control()
594 DPU_REG_WRITE(c, CTL_TOP, mode_sel); in dpu_hw_ctl_intf_cfg_v1()
601 DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, in dpu_hw_ctl_intf_cfg_v1()
[all …]
H A Ddpu_hw_wb.c115 DPU_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF); in dpu_hw_wb_setup_format()
116 DPU_REG_WRITE(c, WB_DST_FORMAT, dst_format); in dpu_hw_wb_setup_format()
117 DPU_REG_WRITE(c, WB_DST_OP_MODE, opmode); in dpu_hw_wb_setup_format()
118 DPU_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern); in dpu_hw_wb_setup_format()
119 DPU_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0); in dpu_hw_wb_setup_format()
120 DPU_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1); in dpu_hw_wb_setup_format()
121 DPU_REG_WRITE(c, WB_OUT_SIZE, outsize); in dpu_hw_wb_setup_format()
135 DPU_REG_WRITE(c, WB_OUT_IMAGE_SIZE, image_size); in dpu_hw_wb_roi()
136 DPU_REG_WRITE(c, WB_OUT_XY, out_xy); in dpu_hw_wb_roi()
137 DPU_REG_WRITE(c, WB_OUT_SIZE, out_size); in dpu_hw_wb_roi()
[all …]
H A Ddpu_hw_cdm.c98 DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_0, in dpu_hw_cdm_setup_cdwn()
100 DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_1, in dpu_hw_cdm_setup_cdwn()
102 DPU_REG_WRITE(c, CDM_CDWN2_COEFF_COSITE_H_2, in dpu_hw_cdm_setup_cdwn()
108 DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_0, in dpu_hw_cdm_setup_cdwn()
110 DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_1, in dpu_hw_cdm_setup_cdwn()
112 DPU_REG_WRITE(c, CDM_CDWN2_COEFF_OFFSITE_H_2, in dpu_hw_cdm_setup_cdwn()
138 DPU_REG_WRITE(c, in dpu_hw_cdm_setup_cdwn()
146 DPU_REG_WRITE(c, in dpu_hw_cdm_setup_cdwn()
164 DPU_REG_WRITE(c, CDM_CDWN2_OP_MODE, opmode); in dpu_hw_cdm_setup_cdwn()
202 DPU_REG_WRITE(c, CDM_CSC_10_OPMODE, csc); in dpu_hw_cdm_enable()
[all …]
H A Ddpu_hw_pingpong.c56 DPU_REG_WRITE(c, base + PP_DITHER_EN, 0); in dpu_hw_pp_setup_dither()
75 DPU_REG_WRITE(c, base + PP_DITHER_EN, 1); in dpu_hw_pp_setup_dither()
94 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); in dpu_hw_pp_enable_te()
99 DPU_REG_WRITE(c, PP_SYNC_THRESH, in dpu_hw_pp_enable_te()
102 DPU_REG_WRITE(c, PP_SYNC_WRCOUNT, in dpu_hw_pp_enable_te()
105 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, 1); in dpu_hw_pp_enable_te()
113 DPU_REG_WRITE(&pp->hw, PP_AUTOREFRESH_CONFIG, in dpu_hw_pp_setup_autorefresh_config()
141 DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, 0); in dpu_hw_pp_disable_te()
162 DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); in dpu_hw_pp_connect_external_te()
264 DPU_REG_WRITE(c, PP_DSC_MODE, 1); in dpu_hw_pp_dsc_enable()
[all …]
H A Ddpu_hw_sspp.c276 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, in dpu_hw_sspp_setup_format()
282 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
289 DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, in dpu_hw_sspp_setup_format()
325 DPU_REG_WRITE(c, op_mode_off, opmode); in dpu_hw_sspp_setup_format()
441 DPU_REG_WRITE(c, src_xy_off, src_xy); in dpu_hw_sspp_setup_rects()
443 DPU_REG_WRITE(c, out_xy_off, dst_xy); in dpu_hw_sspp_setup_rects()
461 DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR, in dpu_hw_sspp_setup_sourceaddress()
463 DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR, in dpu_hw_sspp_setup_sourceaddress()
466 DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR, in dpu_hw_sspp_setup_sourceaddress()
468 DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR, in dpu_hw_sspp_setup_sourceaddress()
[all …]
H A Ddpu_hw_lm.c60 DPU_REG_WRITE(c, LM_OUT_SIZE, outsize); in dpu_hw_lm_setup_out()
67 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_out()
77 DPU_REG_WRITE(c, LM_BORDER_COLOR_0, in dpu_hw_lm_setup_border_color()
80 DPU_REG_WRITE(c, LM_BORDER_COLOR_1, in dpu_hw_lm_setup_border_color()
111 DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA + stage_off, const_alpha); in dpu_hw_lm_setup_blend_config_combined_alpha()
112 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config_combined_alpha()
128 DPU_REG_WRITE(c, LM_BLEND0_FG_ALPHA + stage_off, fg_alpha); in dpu_hw_lm_setup_blend_config()
129 DPU_REG_WRITE(c, LM_BLEND0_BG_ALPHA + stage_off, bg_alpha); in dpu_hw_lm_setup_blend_config()
130 DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); in dpu_hw_lm_setup_blend_config()
144 DPU_REG_WRITE(c, LM_OP_MODE, op_mode); in dpu_hw_lm_setup_color3()
H A Ddpu_hw_top.c64 DPU_REG_WRITE(c, SSPP_SPARE, cfg->split_flush_en ? 0x1 : 0x0); in dpu_hw_setup_split_pipe()
65 DPU_REG_WRITE(c, SPLIT_DISPLAY_LOWER_PIPE_CTRL, lower_pipe); in dpu_hw_setup_split_pipe()
66 DPU_REG_WRITE(c, SPLIT_DISPLAY_UPPER_PIPE_CTRL, upper_pipe); in dpu_hw_setup_split_pipe()
67 DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1); in dpu_hw_setup_split_pipe()
154 DPU_REG_WRITE(c, wd_load_value, in dpu_hw_setup_wd_timer()
157 DPU_REG_WRITE(c, wd_ctl, BIT(0)); /* clear timer */ in dpu_hw_setup_wd_timer()
161 DPU_REG_WRITE(c, wd_ctl2, reg); in dpu_hw_setup_wd_timer()
190 DPU_REG_WRITE(c, MDP_VSYNC_SEL, reg); in dpu_hw_setup_vsync_sel()
233 DPU_REG_WRITE(c, HDMI_DP_CORE_SELECT, 0x1); in dpu_hw_intf_audio_select()
263 DPU_REG_WRITE(c, MDP_DP_PHY_INTF_SEL, sel); in dpu_hw_dp_phy_intf_sel()
H A Ddpu_hw_vbif.c54 DPU_REG_WRITE(c, VBIF_XIN_CLR_ERR, pnd | src); in dpu_hw_clear_errors()
84 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
105 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
143 DPU_REG_WRITE(c, VBIF_XIN_HALT_CTRL0, reg_val); in dpu_hw_set_halt_ctrl()
183 DPU_REG_WRITE(c, VBIF_XINL_QOS_RP_REMAP_000 + reg_high, reg_val); in dpu_hw_set_qos_remap()
184 DPU_REG_WRITE(c, reg_lvl + reg_high, reg_val_lvl); in dpu_hw_set_qos_remap()
199 DPU_REG_WRITE(c, VBIF_WRITE_GATHER_EN, reg_val); in dpu_hw_set_write_gather_en()
H A Ddpu_hw_merge3d.c28 DPU_REG_WRITE(c, MERGE_3D_MODE, 0); in dpu_hw_merge_3d_setup_3d_mode()
29 DPU_REG_WRITE(c, MERGE_3D_MUX, 0); in dpu_hw_merge_3d_setup_3d_mode()
32 DPU_REG_WRITE(c, MERGE_3D_MODE, data); in dpu_hw_merge_3d_setup_3d_mode()
H A Ddpu_hw_interrupts.c272 DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, in dpu_core_irq()
345 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_enable_irq_locked()
347 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_enable_irq_locked()
397 DPU_REG_WRITE(&intr->hw, reg->en_off, cache_irq_mask); in dpu_hw_intr_disable_irq_locked()
399 DPU_REG_WRITE(&intr->hw, reg->clr_off, DPU_IRQ_MASK(irq_idx)); in dpu_hw_intr_disable_irq_locked()
424 DPU_REG_WRITE(&intr->hw, in dpu_clear_irqs()
442 DPU_REG_WRITE(&intr->hw, in dpu_disable_all_irqs()
479 DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, in dpu_core_irq_read()
H A Ddpu_hw_cwb.c44 DPU_REG_WRITE(c, CWB_MUX, cwb_mux_cfg); in dpu_hw_cwb_config()
45 DPU_REG_WRITE(c, CWB_MODE, input); in dpu_hw_cwb_config()
H A Ddpu_hw_util.h339 #define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off) macro