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Searched refs:DPU_CLK_CTRL_DMA0 (Results 1 – 25 of 26) sorted by relevance

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/linux-6.15/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_6_3_sm6115.h24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
53 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_6_5_qcm2290.h24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
53 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_6_9_sm6375.h25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
54 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_4_1_sdm670.h18 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
48 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_1_15_msm8917.h27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
78 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_1_14_msm8937.h27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
78 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_1_16_msm8953.h27 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
78 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_5_4_sm6125.h28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
84 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_6_2_sc7180.h24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
66 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_3_3_sdm630.h28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
77 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_6_4_sm6350.h26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
74 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_7_2_sc7280.h24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
71 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_5_3_sm6150.h26 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
84 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_3_2_sdm660.h29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
86 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_3_0_msm8998.h32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
107 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_5_2_sm7150.h30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
95 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_1_7_msm8996.h35 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
134 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_4_0_sdm845.h32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
105 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_5_0_sm8150.h32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
115 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_6_0_sm8250.h29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
113 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_7_0_sm8350.h29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
113 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_5_1_sc8180x.h32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
114 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_8_1_sm8450.h30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
114 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_8_0_sc8280xp.h30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
113 .clk_ctrl = DPU_CLK_CTRL_DMA0,
H A Ddpu_8_4_sa8775p.h29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
113 .clk_ctrl = DPU_CLK_CTRL_DMA0,

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