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Searched refs:DPLL_VCO_ENABLE (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/gma500/
H A Doaktrail_crtc.c246 if ((temp & DPLL_VCO_ENABLE) == 0) { in oaktrail_crtc_dpms()
252 temp | DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
257 temp | DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
318 if ((temp & DPLL_VCO_ENABLE) != 0) { in oaktrail_crtc_dpms()
320 temp & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_dpms()
530 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
554 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set()
556 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set()
559 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set()
H A Dgma_display.c224 if ((temp & DPLL_VCO_ENABLE) == 0) { in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
312 if ((temp & DPLL_VCO_ENABLE) != 0) { in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
633 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) { in gma_crtc_restore()
635 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in gma_crtc_restore()
H A Dpsb_intel_display.c209 dpll |= DPLL_VCO_ENABLE; in psb_intel_crtc_mode_set()
218 if (dpll & DPLL_VCO_ENABLE) { in psb_intel_crtc_mode_set()
220 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
H A Dcdv_intel_display.c758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
H A Dpsb_intel_reg.h229 #define DPLL_VCO_ENABLE (1 << 31) macro
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c526 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
554 if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
1012 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i9xx_dpll()
1105 dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS; in i8xx_dpll()
1283 dpll = DPLL_VCO_ENABLE; in ilk_dpll()
1445 dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV; in vlv_dpll()
1471 dpll |= DPLL_VCO_ENABLE; in chv_dpll()
2034 hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); in vlv_enable_pll()
2036 if (hw_state->dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
2181 hw_state->dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
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H A Dintel_pch_refclk.c538 if (!(temp & DPLL_VCO_ENABLE)) in ilk_init_pch_refclk()
H A Dintel_display_power_well.c1378 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
H A Dintel_pps.c127 pll_enabled = intel_de_read(display, DPLL(display, pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
H A Dintel_dpll_mgr.c546 return val & DPLL_VCO_ENABLE; in ibx_pch_dpll_get_hw_state()
H A Dintel_display.c8159 DPLL_VCO_ENABLE; in i830_enable_pipe()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_reg.h727 #define DPLL_VCO_ENABLE (1 << 31) macro