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Searched refs:DPIO_PHY1 (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c1135 MMIO_D(BXT_PHY_CTL_FAMILY(DPIO_PHY1)); in iterate_bxt_mmio()
1151 MMIO_D(BXT_PORT_CL1CM_DW0(DPIO_PHY1)); in iterate_bxt_mmio()
1152 MMIO_D(BXT_PORT_CL1CM_DW9(DPIO_PHY1)); in iterate_bxt_mmio()
1153 MMIO_D(BXT_PORT_CL1CM_DW10(DPIO_PHY1)); in iterate_bxt_mmio()
1154 MMIO_D(BXT_PORT_CL1CM_DW28(DPIO_PHY1)); in iterate_bxt_mmio()
1155 MMIO_D(BXT_PORT_CL1CM_DW30(DPIO_PHY1)); in iterate_bxt_mmio()
1156 MMIO_D(BXT_PORT_CL2CM_DW6(DPIO_PHY1)); in iterate_bxt_mmio()
1157 MMIO_D(BXT_PORT_REF_DW3(DPIO_PHY1)); in iterate_bxt_mmio()
1158 MMIO_D(BXT_PORT_REF_DW6(DPIO_PHY1)); in iterate_bxt_mmio()
1159 MMIO_D(BXT_PORT_REF_DW8(DPIO_PHY1)); in iterate_bxt_mmio()
[all …]
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_display_power_well.c1350 if (!display->power.chv_phy_assert[DPIO_PHY1]) in assert_chv_phy_status()
1352 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | in assert_chv_phy_status()
1353 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); in assert_chv_phy_status()
1397 phy_status |= PHY_POWERGOOD(DPIO_PHY1); in assert_chv_phy_status()
1404 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) in assert_chv_phy_status()
1405 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); in assert_chv_phy_status()
1408 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) in assert_chv_phy_status()
1409 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); in assert_chv_phy_status()
1411 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) in assert_chv_phy_status()
1446 phy = DPIO_PHY1; in chv_dpio_cmn_power_well_enable()
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H A Dintel_dpio_phy.c170 .rcomp_phy = DPIO_PHY1,
178 [DPIO_PHY1] = {
192 .rcomp_phy = DPIO_PHY1,
200 [DPIO_PHY1] = {
212 .rcomp_phy = DPIO_PHY1,
683 return DPIO_PHY1; in vlv_dig_port_to_phy()
697 return DPIO_PHY1; in vlv_pipe_to_phy()
H A Dintel_dpio_phy.h25 DPIO_PHY1, enumerator
H A Dintel_display_power.c1768 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | in chv_phy_control_init()
1771 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1821 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1824 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); in chv_phy_control_init()
1826 display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
1828 display->power.chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
1830 display->power.chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
H A Dintel_display_power_map.c478 .bxt.phy = DPIO_PHY1,
581 .bxt.phy = DPIO_PHY1,
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dmmio.c268 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
272 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= in intel_vgpu_reset_mmio()
H A Ddisplay.c247 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in emulate_monitor_status_change()
250 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30); in emulate_monitor_status_change()
279 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in emulate_monitor_status_change()
281 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |= in emulate_monitor_status_change()
H A Dhandlers.c556 phy = DPIO_PHY1; in bxt_vgpu_get_dp_bitrate()
1903 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &= in bxt_gt_disp_pwron_write()
1905 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |= in bxt_gt_disp_pwron_write()
2777 MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT, in init_bxt_mmio_info()
2794 MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT, in init_bxt_mmio_info()
2796 MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT, in init_bxt_mmio_info()