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Searched refs:DLL (Results 1 – 25 of 28) sorted by relevance

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/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
80 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_gddr3_calc()
89 DLL = !(ram->mr[1] & 0x1); in nvkm_gddr3_calc()
117 ram->mr[1] |= !DLL << 6; in nvkm_gddr3_calc()
H A Dsddr2.c63 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
69 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr2_calc()
98 ram->mr[1] |= !DLL; in nvkm_sddr2_calc()
H A Dsddr3.c72 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
74 DLL = !ram->next->bios.ramcfg_DLLoff; in nvkm_sddr3_calc()
115 ram->mr[1] |= !DLL; in nvkm_sddr3_calc()
/linux-6.15/arch/arm/mach-omap2/
H A Dsleep24xx.S60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
H A Dsram243x.S52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
H A Dsram242x.S52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
/linux-6.15/arch/x86/boot/
H A Dearly_serial_console.c21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL); in early_serial_init()
109 dll = inb(port + DLL); in probe_baud()
/linux-6.15/tools/testing/kunit/
H A D.gitignore2 # Byte-compiled / optimized / DLL files
/linux-6.15/Documentation/devicetree/bindings/mmc/
H A Dhisilicon,hi3798cv200-dw-mshc.yaml41 DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path.
45 - description: Sample DLL register offset in CRG address space
H A Dsdhci-st.txt27 to configure DLL inside the flashSS, if so reg-names must also be
32 for eMMC on stih407 family silicon to configure DLL inside FlashSS.
H A Dcdns,sdhci.yaml35 # PHY DLL input delays:
85 # PHY DLL clock delays:
H A Dfsl-imx-esdhc.yaml114 This is used to set the clock delay for DLL(Delay Line) on override mode
117 chapter, DLL (Delay Line) section in RM for details.
H A Dsdhci-am654.yaml174 description: DLL trim select
180 description: DLL drive strength in ohms
H A Dsprd,sdhci-r11.yaml61 PHY DLL delays are used to delay the data valid window, and align
/linux-6.15/arch/arm/mach-orion5x/
H A Dtsx09-common.c33 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off()
H A Dterastation_pro2-setup.c276 writel(divisor & 0xff, UART1_REG(DLL)); in tsp2_power_off()
H A Dkurobox_pro-setup.c298 writel(divisor & 0xff, UART1_REG(DLL)); in kurobox_pro_power_off()
/linux-6.15/drivers/usb/serial/
H A Dio_16654.h40 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB macro
/linux-6.15/Documentation/misc-devices/
H A Doxsemi-tornado.rst94 and the clock divisor (DLM/DLL) as follows to obtain such rates if so
101 |0 0 0| CPR2:CPR | TCR | DLM:DLL |
112 For example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL
/linux-6.15/drivers/power/reset/
H A Dqnap-poweroff.c61 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_power_off()
/linux-6.15/arch/x86/kernel/
H A Dearly_printk.c95 #define DLL 0 /* Divisor Latch Low */ macro
144 static_call(serial_out)(early_serial_base, DLL, divisor & 0xff); in early_serial_hw_init()
/linux-6.15/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
110 Note: if DLL was bypassed, the odt will also stop working.
117 is less than DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
118 Note: PHY DLL and PHY ODT are independent.
/linux-6.15/Documentation/devicetree/bindings/net/
H A Dmicrochip,sparx5-switch.yaml135 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
144 the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and
/linux-6.15/drivers/net/hamradio/
H A Dbaycom_ser_fdx.c102 #define DLL(iobase) (iobase+0) macro
174 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()
H A Dbaycom_ser_hdx.c88 #define DLL(iobase) (iobase+0) macro
159 outb(divisor, DLL(dev->base_addr)); in ser12_set_divisor()

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