DIV_CLK_MPLL_AXI_DDR_0 (reference) in projects: linux-6.15

Searched refs:DIV_CLK_MPLL_AXI_DDR_0 (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/include/dt-bindings/clock/
H A D	sophgo,sg2042-clkgen.h	`10 #define DIV_CLK_MPLL_AXI_DDR_0 1 macro`
/linux-6.15/drivers/clk/sophgo/
H A D	clk-sg2042-clkgen.c	`492 SG2042_DIV_HWS(DIV_CLK_MPLL_AXI_DDR_0,`