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Searched refs:DISP_CC_MDSS_PCLK0_CLK_SRC (Results 1 – 25 of 62) sorted by relevance

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/linux-6.15/include/dt-bindings/clock/
H A Dqcom,dispcc-qcm2290.h24 #define DISP_CC_MDSS_PCLK0_CLK_SRC 14 macro
H A Dqcom,sm6115-dispcc.h25 #define DISP_CC_MDSS_PCLK0_CLK_SRC 15 macro
H A Dqcom,sm6375-dispcc.h25 #define DISP_CC_MDSS_PCLK0_CLK_SRC 14 macro
H A Dqcom,dispcc-sm6125.h31 #define DISP_CC_MDSS_PCLK0_CLK_SRC 22 macro
H A Dqcom,dispcc-sc7180.h34 #define DISP_CC_MDSS_PCLK0_CLK_SRC 25 macro
H A Dqcom,dispcc-sm6350.h35 #define DISP_CC_MDSS_PCLK0_CLK_SRC 24 macro
H A Dqcom,sm4450-dispcc.h26 #define DISP_CC_MDSS_PCLK0_CLK_SRC 16 macro
H A Dqcom,dispcc-sdm845.h26 #define DISP_CC_MDSS_PCLK0_CLK_SRC 16 macro
H A Dqcom,dispcc-sc7280.h42 #define DISP_CC_MDSS_PCLK0_CLK_SRC 32 macro
H A Dqcom,dispcc-sm8150.h47 #define DISP_CC_MDSS_PCLK0_CLK_SRC 37 macro
H A Dqcom,dispcc-sm8250.h47 #define DISP_CC_MDSS_PCLK0_CLK_SRC 37 macro
H A Dqcom,dispcc-sm8350.h47 #define DISP_CC_MDSS_PCLK0_CLK_SRC 37 macro
H A Dqcom,dispcc-sc8280xp.h76 #define DISP_CC_MDSS_PCLK0_CLK_SRC 66 macro
H A Dqcom,x1e80100-dispcc.h74 #define DISP_CC_MDSS_PCLK0_CLK_SRC 64 macro
H A Dqcom,sm8450-dispcc.h76 #define DISP_CC_MDSS_PCLK0_CLK_SRC 66 macro
H A Dqcom,sm8650-dispcc.h77 #define DISP_CC_MDSS_PCLK0_CLK_SRC 67 macro
H A Dqcom,sm8550-dispcc.h77 #define DISP_CC_MDSS_PCLK0_CLK_SRC 67 macro
H A Dqcom,sm8750-dispcc.h83 #define DISP_CC_MDSS_PCLK0_CLK_SRC 71 macro
/linux-6.15/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6115-mdss.yaml158 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
H A Dqcom,sm6375-mdss.yaml170 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
H A Dqcom,sm6125-mdss.yaml171 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
H A Dqcom,qcm2290-mdss.yaml167 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
H A Dqcom,sm6350-mdss.yaml178 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
H A Dqcom,sm8350-mdss.yaml209 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
H A Dqcom,sdm845-mdss.yaml169 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;

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