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Searched refs:DISP_CC_MDSS_CORE_BCR (Results 1 – 25 of 33) sorted by relevance

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/linux-6.15/include/dt-bindings/clock/
H A Dqcom,dispcc-qcm2290.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm6375-dispcc.h36 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm4450-dispcc.h47 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8150.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8250.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sm8350.h70 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,dispcc-sc8280xp.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,x1e80100-dispcc.h90 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8450-dispcc.h95 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8650-dispcc.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8550-dispcc.h93 #define DISP_CC_MDSS_CORE_BCR 0 macro
H A Dqcom,sm8750-dispcc.h104 #define DISP_CC_MDSS_CORE_BCR 0 macro
/linux-6.15/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sc8280xp-mdss.yaml77 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8350-mdss.yaml104 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8550-mdss.yaml102 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
H A Dqcom,sm8450-mdss.yaml101 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
/linux-6.15/drivers/clk/qcom/
H A Ddispcc-qcm2290.c448 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
H A Ddispcc-sm6375.c545 [DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
H A Ddispcc-sm4450.c711 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sm8250.c1220 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
H A Ddispcc-x1e80100.c1620 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sm8550.c1730 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sm8450.c1764 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sm8750.c1870 [DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
H A Ddispcc-sc8280xp.c3046 [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },

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