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Searched refs:DISPLAY_VER (Results 1 – 25 of 87) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_display_device.h158 #define HAS_DOUBLE_WIDE(__display) (DISPLAY_VER(__display) < 4)
161 #define HAS_DPT(__display) (DISPLAY_VER(__display) >= 13)
169 #define HAS_FW_BLC(__display) (DISPLAY_VER(__display) >= 3)
170 #define HAS_GMBUS_IRQ(__display) (DISPLAY_VER(__display) >= 4)
176 #define HAS_LRR(__display) (DISPLAY_VER(__display) >= 12)
179 #define HAS_MSO(__display) (DISPLAY_VER(__display) >= 12)
184 #define HAS_SAGV(__display) (DISPLAY_VER(__display) >= 9 && \
192 #define HAS_VRR(__display) (DISPLAY_VER(__display) >= 11)
193 #define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)
194 #define HAS_CMRR(__display) (DISPLAY_VER(__display) >= 20)
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H A Di9xx_display_sr.c20 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_save_swf()
27 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_save_swf()
45 if (DISPLAY_VER(display) == 2 && display->platform.mobile) { in i9xx_display_restore_swf()
52 } else if (DISPLAY_VER(display) == 2) { in i9xx_display_restore_swf()
73 if (DISPLAY_VER(display) <= 4) in i9xx_display_sr_save()
76 if (DISPLAY_VER(display) == 4) in i9xx_display_sr_save()
91 if (DISPLAY_VER(display) == 4) in i9xx_display_sr_restore()
95 if (DISPLAY_VER(display) <= 4) in i9xx_display_sr_restore()
H A Di9xx_plane.c213 if (DISPLAY_VER(display) >= 4 && in i9xx_plane_ctl()
256 if (DISPLAY_VER(display) >= 4) in i9xx_check_plane_surface()
371 if (DISPLAY_VER(display) < 5) in i9xx_plane_ctl_crtc()
435 if (DISPLAY_VER(display) < 4) { in i9xx_plane_update_noarm()
473 if (DISPLAY_VER(display) >= 4) in i9xx_plane_update_arm()
509 if (DISPLAY_VER(display) >= 4) in i9xx_plane_update_arm()
554 if (DISPLAY_VER(display) >= 4) in i9xx_plane_disable_arm()
743 if (DISPLAY_VER(display) >= 5) in i9xx_plane_get_hw_state()
962 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
1079 if (DISPLAY_VER(display) >= 4) in intel_primary_plane_create()
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H A Dintel_fbc.c173 if (DISPLAY_VER(display) >= 11) in skl_fbc_min_cfb_stride()
196 if (DISPLAY_VER(display) >= 9) in _intel_fbc_cfb_stride()
219 if (DISPLAY_VER(display) >= 8) in intel_fbc_max_cfb_height()
279 if (DISPLAY_VER(display) == 2) in i8xx_fbc_ctl()
342 if (DISPLAY_VER(display) == 4) { in i8xx_fbc_activate()
451 if (DISPLAY_VER(display) < 6) in g4x_dpfc_ctl()
642 if (DISPLAY_VER(display) >= 20) in ivb_dpfc_ctl()
659 if (DISPLAY_VER(display) >= 10) in ivb_fbc_activate()
669 if (DISPLAY_VER(display) >= 20) in ivb_fbc_activate()
1104 if (DISPLAY_VER(display) >= 9) in rotation_is_valid()
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H A Dintel_wm.c159 if (DISPLAY_VER(dev_priv) >= 9) in intel_print_wm_latency()
172 if (DISPLAY_VER(i915) >= 9) in intel_wm_init()
192 if (DISPLAY_VER(dev_priv) >= 9 || in wm_latency_show()
212 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_show()
227 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_show()
242 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_show()
256 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) in pri_wm_latency_open()
323 if (DISPLAY_VER(dev_priv) >= 9) in pri_wm_latency_write()
338 if (DISPLAY_VER(dev_priv) >= 9) in spr_wm_latency_write()
353 if (DISPLAY_VER(dev_priv) >= 9) in cur_wm_latency_write()
H A Dskl_universal_plane.c862 if (DISPLAY_VER(display) < 11) in skl_write_plane_wm()
866 if (DISPLAY_VER(display) >= 30) in skl_write_plane_wm()
1157 if (DISPLAY_VER(display) >= 10) in skl_plane_ctl_crtc()
1195 if (DISPLAY_VER(display) >= 11) in skl_plane_ctl()
1205 if (DISPLAY_VER(display) == 13) in skl_plane_ctl()
1216 if (DISPLAY_VER(display) >= 11) in glk_plane_color_ctl_crtc()
1316 if (DISPLAY_VER(display) < 12) in skl_plane_aux_dist()
1436 if (DISPLAY_VER(display) >= 10) in skl_plane_update_arm()
1457 if (DISPLAY_VER(display) >= 10) in skl_plane_update_arm()
2069 if (DISPLAY_VER(display) >= 13) in skl_check_main_surface()
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H A Dintel_psr.c318 if (DISPLAY_VER(display) >= 8) in psr_ctl_reg()
327 if (DISPLAY_VER(display) >= 8) in psr_debug_reg()
336 if (DISPLAY_VER(display) >= 8) in psr_perf_cnt_reg()
345 if (DISPLAY_VER(display) >= 8) in psr_status_reg()
354 if (DISPLAY_VER(display) >= 12) in psr_imr_reg()
363 if (DISPLAY_VER(display) >= 12) in psr_iir_reg()
372 if (DISPLAY_VER(display) >= 8) in psr_aux_ctl_reg()
381 if (DISPLAY_VER(display) >= 8) in psr_aux_data_reg()
1026 if (DISPLAY_VER(display) >= 10 && DISPLAY_VER(display) < 13) in hsw_activate_psr2()
1033 if (DISPLAY_VER(display) >= 12 && DISPLAY_VER(display) < 20) { in hsw_activate_psr2()
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H A Dintel_alpm.c179 if (DISPLAY_VER(display) < 20) in _lnl_compute_alpm_params()
219 if (DISPLAY_VER(display) >= 12) in io_buffer_wake_time()
241 if (DISPLAY_VER(display) >= 20) in intel_alpm_compute_params()
243 else if (DISPLAY_VER(display) >= 12) in intel_alpm_compute_params()
282 if (DISPLAY_VER(display) < 20) in intel_alpm_lobf_compute_config()
319 if (DISPLAY_VER(display) < 20 || in lnl_alpm_configure()
411 if (DISPLAY_VER(display) < 20 || in intel_alpm_lobf_debugfs_add()
H A Dintel_ddi.c185 if (DISPLAY_VER(display) >= 14) in intel_ddi_buf_status_reg()
226 if (DISPLAY_VER(display) < 10) { in intel_wait_ddi_buf_active()
362 if (DISPLAY_VER(i915) >= 14) { in intel_ddi_init_dp_buf_reg()
519 if (DISPLAY_VER(dev_priv) >= 12) in intel_ddi_transcoder_func_reg_val_get()
684 if (DISPLAY_VER(dev_priv) >= 11) in intel_ddi_disable_transcoder_func()
2417 if (DISPLAY_VER(display) < 30) in intel_ddi_enable_fec()
2479 if (DISPLAY_VER(i915) > 20) in intel_ddi_splitter_pipe_mask()
3109 if (DISPLAY_VER(display) < 14) in intel_ddi_buf_disable()
4630 if (DISPLAY_VER(i915) >= 14) in intel_ddi_init_dp_connector()
4973 if (DISPLAY_VER(i915) >= 12) in intel_ddi_is_tc()
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H A Dintel_pmdemand.c150 if (DISPLAY_VER(display) < 14) in intel_pmdemand_update_phys_mask()
172 if (DISPLAY_VER(display) < 14) in intel_pmdemand_update_port_clock()
315 if (DISPLAY_VER(display) < 30) { in intel_pmdemand_needs_update()
347 if (DISPLAY_VER(display) < 14) in intel_pmdemand_atomic_check()
369 if (DISPLAY_VER(display) < 30) { in intel_pmdemand_atomic_check()
427 if (DISPLAY_VER(display) < 14) in intel_pmdemand_init_pmdemand_params()
456 if (DISPLAY_VER(display) >= 30) { in intel_pmdemand_init_pmdemand_params()
495 if (DISPLAY_VER(display) >= 30) in intel_pmdemand_program_dbuf()
559 if (DISPLAY_VER(display) >= 30) { in intel_pmdemand_update_params()
639 if (DISPLAY_VER(display) < 14) in intel_pmdemand_pre_plane_update()
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H A Dintel_display_irq.c285 if (DISPLAY_VER(display) < 5) in i915_pipestat_enable_mask()
399 if (DISPLAY_VER(dev_priv) >= 4) in i915_enable_asle_pipestat()
496 if (DISPLAY_VER(dev_priv) >= 3) in i9xx_pipe_crc_irq_handler()
1003 if (DISPLAY_VER(dev_priv) >= 20) in gen8_de_port_aux_mask()
1030 if (DISPLAY_VER(dev_priv) >= 9) in gen8_de_port_aux_mask()
1047 if (DISPLAY_VER(display) >= 14) in gen8_de_pipe_fault_mask()
1186 if (DISPLAY_VER(display) >= 14) in gen8_pipe_fault_handlers()
1327 if (DISPLAY_VER(i915) >= 9) in gen8_de_pipe_flip_done_mask()
2048 if (DISPLAY_VER(dev_priv) >= 14) in gen11_display_irq_reset()
2164 if (DISPLAY_VER(i915) >= 7) { in ilk_de_irq_postinstall()
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H A Dintel_bw.c156 if (DISPLAY_VER(dev_priv) >= 14) in icl_pcode_restrict_qgv_points()
207 if (DISPLAY_VER(dev_priv) >= 14) in intel_read_qgv_point_info()
737 if (DISPLAY_VER(i915) >= 12) in icl_qgv_bw()
802 if (DISPLAY_VER(i915) < 11) in intel_bw_crtc_data_rate()
815 if (DISPLAY_VER(i915) < 12) in intel_bw_crtc_min_cdclk()
1126 if (DISPLAY_VER(i915) >= 14) in intel_bw_check_qgv_points()
1206 if (DISPLAY_VER(i915) < 11) in skl_crtc_calc_dbuf_bw()
1270 if (DISPLAY_VER(dev_priv) < 9) in intel_bw_calc_min_cdclk()
1387 if (DISPLAY_VER(i915) < 11) in intel_bw_atomic_check()
1443 if (DISPLAY_VER(display) < 9) in intel_bw_update_hw_state()
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H A Dskl_watermark.c74 return DISPLAY_VER(i915) == 9; in skl_needs_memory_bw_wa()
129 if (DISPLAY_VER(display) < 11) in intel_sagv_init()
328 if (DISPLAY_VER(i915) >= 11) in intel_sagv_pre_plane_update()
348 if (DISPLAY_VER(i915) >= 11) in intel_sagv_post_plane_update()
434 if (DISPLAY_VER(i915) >= 12) in intel_crtc_can_enable_sagv()
443 if (DISPLAY_VER(i915) < 11 && in intel_can_enable_sagv()
489 DISPLAY_VER(i915) >= 12 && in intel_compute_sagv_mask()
1978 if (DISPLAY_VER(i915) < 30) in skl_compute_plane_wm()
2127 if (DISPLAY_VER(i915) == 9) in skl_compute_transition_wm()
3034 if ((DISPLAY_VER(display) == 20 || DISPLAY_VER(display) == 30) && !latency) { in intel_program_dpkgc_latency()
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H A Dintel_display_power.c932 if (DISPLAY_VER(display) >= 20) in get_allowed_dc_mask()
1098 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_enable()
1112 if (DISPLAY_VER(display) >= 14) in gen9_dbuf_disable()
1148 if (DISPLAY_VER(display) == 12) in icl_mbus_init()
1417 if (DISPLAY_VER(display) >= 14) in intel_pch_reset_handshake()
1624 if (DISPLAY_VER(display) == 12) in tgl_bw_buddy_init()
1665 if (DISPLAY_VER(display) == 14) in icl_display_core_init()
1682 if (DISPLAY_VER(display) >= 12) in icl_display_core_init()
1703 if (DISPLAY_VER(display) == 13) in icl_display_core_init()
1734 if (DISPLAY_VER(display) == 14) in icl_display_core_uninit()
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H A Dintel_display_wa.c36 else if (DISPLAY_VER(i915) == 12) in intel_display_wa_apply()
38 else if (DISPLAY_VER(i915) == 11) in intel_display_wa_apply()
H A Dintel_dpt_common.c17 if (DISPLAY_VER(i915) == 14) { in intel_dpt_configure()
30 } else if (DISPLAY_VER(i915) == 13) { in intel_dpt_configure()
H A Dintel_cmtg.c66 return DISPLAY_VER(display) >= 20; in intel_cmtg_has_cmtg_b()
71 return DISPLAY_VER(display) >= 14; in intel_cmtg_has_clock_sel()
123 if (DISPLAY_VER(display) >= 20) in intel_cmtg_disable_requires_modeset()
H A Dintel_sprite_uapi.c13 return DISPLAY_VER(dev_priv) >= 9; in has_dst_key_in_primary_plane()
37 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && in intel_plane_set_ckey()
77 if (DISPLAY_VER(dev_priv) >= 9 && in intel_sprite_set_colorkey_ioctl()
H A Dintel_pfit.c77 if (DISPLAY_VER(display) >= 8) { in intel_pch_pfit_check_src_size()
80 } else if (DISPLAY_VER(display) >= 7) { in intel_pch_pfit_check_src_size()
259 if (DISPLAY_VER(display) >= 9) in pch_panel_fitting()
426 if (DISPLAY_VER(display) >= 4) in intel_gmch_pfit_check_timings()
496 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
510 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
526 if (DISPLAY_VER(display) >= 4) in gmch_panel_fitting()
536 if (DISPLAY_VER(display) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
690 return DISPLAY_VER(display) >= 4 || in i9xx_has_pfit()
709 if (DISPLAY_VER(display) >= 4) in i9xx_pfit_get_config()
H A Dintel_crtc.c115 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_crtc_max_vblank_count()
117 else if (DISPLAY_VER(display) >= 3) in intel_crtc_max_vblank_count()
321 if (DISPLAY_VER(display) >= 9) in intel_crtc_init()
336 if (DISPLAY_VER(dev_priv) >= 9) in intel_crtc_init()
359 else if (DISPLAY_VER(display) == 4) in intel_crtc_init()
364 else if (DISPLAY_VER(display) == 3) in intel_crtc_init()
369 if (DISPLAY_VER(display) >= 8) in intel_crtc_init()
381 if (DISPLAY_VER(display) >= 11) in intel_crtc_init()
676 if (DISPLAY_VER(display) >= 11 && in intel_pipe_update_end()
H A Dintel_vrr.c94 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_extra_vblank_delay()
108 return DISPLAY_VER(display) < 13 ? 1 : 0; in intel_vrr_flipline_offset()
138 if (DISPLAY_VER(display) >= 13) in intel_vrr_vblank_exit_length()
150 if (DISPLAY_VER(display) >= 13) in intel_vrr_vmin_vtotal()
161 if (DISPLAY_VER(display) >= 13) in intel_vrr_vmax_vtotal()
320 if (DISPLAY_VER(display) >= 13) { in intel_vrr_compute_config_late()
343 if (DISPLAY_VER(display) >= 13) in trans_vrr_ctl()
523 if (DISPLAY_VER(display) >= 13) in intel_vrr_get_config()
H A Dintel_cx0_phy_regs.h45 (DISPLAY_VER(i915__) >= 20 ? \
65 (DISPLAY_VER(i915__) >= 20 ? \
96 (DISPLAY_VER(i915__) >= 20 ? \
122 (DISPLAY_VER(i915__) >= 20 ? \
145 (DISPLAY_VER(i915__) >= 20 ? \
168 (DISPLAY_VER(i915__) >= 20 ? \
185 (DISPLAY_VER(i915__) >= 20 ? \
H A Dskl_scaler.c97 if (DISPLAY_VER(display) >= 14) { in skl_scaler_max_src_size()
100 } else if (DISPLAY_VER(display) >= 12) { in skl_scaler_max_src_size()
103 } else if (DISPLAY_VER(display) == 11) { in skl_scaler_max_src_size()
123 if (DISPLAY_VER(display) >= 12) { in skl_scaler_max_dst_size()
126 } else if (DISPLAY_VER(display) == 11) { in skl_scaler_max_dst_size()
167 if (DISPLAY_VER(display) >= 9 && crtc_state->hw.enable && in skl_update_scaler()
338 if (DISPLAY_VER(display) >= 14) { in calculate_max_scale()
351 } else if (DISPLAY_VER(display) >= 10 || !is_yuv_semiplanar) { in calculate_max_scale()
385 if (DISPLAY_VER(display) == 9) { in intel_atomic_setup_scaler()
403 } else if (DISPLAY_VER(display) >= 10) { in intel_atomic_setup_scaler()
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H A Dintel_audio.c507 if (DISPLAY_VER(display) < 11) in enable_audio_dsc_wa()
512 if (DISPLAY_VER(display) == 11) in enable_audio_dsc_wa()
910 if (DISPLAY_VER(display) >= 13) in intel_audio_cdclk_change_pre()
924 if (DISPLAY_VER(display) >= 13) { in intel_audio_cdclk_change_post()
1009 if (DISPLAY_VER(display) == 10) { in intel_audio_min_cdclk()
1022 if (DISPLAY_VER(display) >= 9) in intel_audio_min_cdclk()
1050 if (DISPLAY_VER(display) >= 9) { in intel_audio_component_get_power()
1062 if (DISPLAY_VER(display) >= 10) in intel_audio_component_get_power()
1090 if (DISPLAY_VER(display) < 9) in intel_audio_component_codec_wake_override()
1334 if (DISPLAY_VER(display) >= 9) { in intel_audio_component_init()
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H A Dintel_dp_aux.c23 if (DISPLAY_VER(display) >= 13 && aux_ch >= AUX_CH_D_XELPD) in aux_ch_name()
25 else if (DISPLAY_VER(display) >= 12 && aux_ch >= AUX_CH_USBC1) in aux_ch_name()
231 if (DISPLAY_VER(display) >= 14) in skl_get_aux_send_ctl()
780 if (DISPLAY_VER(display) >= 14) { in intel_dp_aux_init()
783 } else if (DISPLAY_VER(display) >= 12) { in intel_dp_aux_init()
786 } else if (DISPLAY_VER(display) >= 9) { in intel_dp_aux_init()
800 if (DISPLAY_VER(display) >= 9) in intel_dp_aux_init()
809 if (DISPLAY_VER(display) >= 9) in intel_dp_aux_init()
831 if (DISPLAY_VER(display) == 9 && encoder->port == PORT_E) in default_aux_ch()

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