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Searched refs:DG1_MSTR_TILE_INTR (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_irq.c401 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, 0); in dg1_intr_disable()
404 val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR); in dg1_intr_disable()
408 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, val); in dg1_intr_disable()
417 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); in dg1_intr_enable()
419 xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR); in dg1_intr_enable()
/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_irq_regs.h14 #define DG1_MSTR_TILE_INTR XE_REG(0x190008) macro
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_irq.c596 raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0); in dg1_master_intr_disable()
599 val = raw_reg_read(regs, DG1_MSTR_TILE_INTR); in dg1_master_intr_disable()
603 raw_reg_write(regs, DG1_MSTR_TILE_INTR, val); in dg1_master_intr_disable()
610 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); in dg1_master_intr_enable()
825 intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); in dg1_irq_postinstall()
H A Di915_reg.h2297 #define DG1_MSTR_TILE_INTR _MMIO(0x190008) macro