Searched refs:DG1_MSTR_TILE (Results 1 – 4 of 4) sorted by relevance
16 #define DG1_MSTR_TILE(t) REG_BIT(t) macro
450 if ((master_tile_ctl & DG1_MSTR_TILE(tile->id)) == 0) in dg1_irq_handler()
631 if (master_tile_ctl & DG1_MSTR_TILE(0)) { in dg1_irq_handler()
2299 #define DG1_MSTR_TILE(t) REG_BIT(t) macro