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Searched refs:DG1_MSTR_IRQ (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_irq_regs.h15 #define DG1_MSTR_IRQ REG_BIT(31) macro
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_irq.c417 xe_mmio_write32(mmio, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); in dg1_intr_enable()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_irq.c610 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); in dg1_master_intr_enable()
H A Di915_reg.h2298 #define DG1_MSTR_IRQ REG_BIT(31) macro