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Searched refs:DCCG_GATE_DISABLE_CNTL5 (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn35/
H A Ddcn35_dccg.h38 SR(DCCG_GATE_DISABLE_CNTL5),\
180 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
181 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
182 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
183 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
200 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\
201 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\
202 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\
203 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\
204 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, mask_sh),\
[all …]
H A Ddcn35_dccg.c279 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_symclk_fe_rcg()
285 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_symclk_fe_rcg()
291 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_symclk_fe_rcg()
297 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_symclk_fe_rcg()
303 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_symclk_fe_rcg()
328 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, in dccg35_set_symclk_be_rcg()
847 REG_GET(DCCG_GATE_DISABLE_CNTL5, in dccg35_is_fe_rcg()
851 REG_GET(DCCG_GATE_DISABLE_CNTL5, in dccg35_is_fe_rcg()
855 REG_GET(DCCG_GATE_DISABLE_CNTL5, in dccg35_is_fe_rcg()
859 REG_GET(DCCG_GATE_DISABLE_CNTL5, in dccg35_is_fe_rcg()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn401/
H A Ddcn401_dccg.h151 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
152 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
153 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
154 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
159 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, mask_sh),\
160 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, mask_sh),\
161 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, mask_sh),\
162 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, mask_sh),\
167 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
168 DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
[all …]
H A Ddcn401_dccg.c490 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg401_enable_dpstreamclk()
499 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg401_enable_dpstreamclk()
508 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg401_enable_dpstreamclk()
517 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg401_enable_dpstreamclk()
543 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg401_disable_dpstreamclk()
551 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg401_disable_dpstreamclk()
559 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg401_disable_dpstreamclk()
567 REG_UPDATE_2(DCCG_GATE_DISABLE_CNTL5, in dccg401_disable_dpstreamclk()
630 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1); in dccg401_set_dp_dto()
638 REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1); in dccg401_set_dp_dto()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.h32 SR(DCCG_GATE_DISABLE_CNTL5), \
H A Ddcn36_resource.c614 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
615 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
616 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
617 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
621 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c633 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
634 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
635 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
636 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
637 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
638 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
639 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
640 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
H A Ddcn35_resource.h171 SR(DCCG_GATE_DISABLE_CNTL5), \
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c613 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
614 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
615 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
616 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
617 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
618 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
619 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
620 HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
/linux-6.15/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.h419 uint32_t DCCG_GATE_DISABLE_CNTL5; \
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.h647 SR(DCCG_GATE_DISABLE_CNTL5),\
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dce/
H A Ddce_hwseq.h694 uint32_t DCCG_GATE_DISABLE_CNTL5; member