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Searched refs:DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h3236 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000f000L macro
H A Dgfx_7_2_sh_mask.h3541 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 macro
H A Dgfx_8_0_sh_mask.h4265 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 macro
H A Dgfx_8_1_sh_mask.h4787 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h14378 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h15681 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h15543 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h17848 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h7798 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h15302 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h19350 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h27633 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h21773 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h21680 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h19877 #define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK … macro