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/linux-6.15/Documentation/hwmon/
H A Dcoretemp.rst5 * All Intel Core family
70 22nm Core i5/i7 Processors
81 32nm Core i3/i5/i7 Processors
88 32nm Core i7 Extreme Processors
103 45nm Xeon Processors 5400 Quad-Core
109 45nm Xeon Processors 5200 Dual-Core
152 45nm Core i3/i5/i7 Processors
172 65nm Core Duo Processors
177 65nm Core Solo Processors
181 65nm Xeon Processors 5000 Quad-Core
[all …]
H A Dk8temp.rst36 temp1_input temperature of Core 0 and "place" 0
37 temp2_input temperature of Core 0 and "place" 1
38 temp3_input temperature of Core 1 and "place" 0
39 temp4_input temperature of Core 1 and "place" 1
H A Dsmpro-hwmon.rst58 temp4_input millicelsius RO Max temperature reported among Core VRDs
76 in0_input millivolts RO Core voltage
81 cur1_input milliamperes RO Core VRD current
86 power1_input microwatts RO Core VRD power
/linux-6.15/Documentation/arch/x86/
H A Dtopology.rst154 1) Single Package, Single Core::
158 2) Single Package, Dual Core
182 -> [Compute Unit Core 1] -> Linux CPU 1
183 -> [Compute Unit 1] -> [Compute Unit Core 0] -> Linux CPU 2
184 -> [Compute Unit Core 1] -> Linux CPU 3
186 4) Dual Package, Dual Core
223 -> [Compute Unit Core 1] -> Linux CPU 1
224 -> [Compute Unit 1] -> [Compute Unit Core 0] -> Linux CPU 2
225 -> [Compute Unit Core 1] -> Linux CPU 3
228 -> [Compute Unit Core 1] -> Linux CPU 5
[all …]
/linux-6.15/Documentation/devicetree/bindings/mips/loongson/
H A Ddevices.yaml20 - description: Classic Loongson64 Quad Core + LS7A
24 - description: Classic Loongson64 Quad Core + RS780E
28 - description: Classic Loongson64 Octa Core + RS780E
32 - description: Generic Loongson64 Quad Core + LS7A
36 - description: Virtual Loongson64 Quad Core + VirtIO
/linux-6.15/drivers/usb/dwc3/
H A DKconfig4 tristate "DesignWare USB3 DRD Core Support"
11 USB controller based on the DesignWare USB3 IP Core.
126 STMicroelectronics SoCs with one DesignWare Core USB3 IP
137 Some Qualcomm SoCs use DesignWare Core IP for USB2/3
149 NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3
158 Support Xilinx SoCs with DesignWare Core USB3 IP.
167 Support TI's AM62 platforms with DesignWare Core USB3 IP.
168 The Designware Core USB3 IP is programmed to operate in
177 Support Cavium Octeon platforms with DesignWare Core USB3 IP.
187 RTK DHC RTD SoCs with DesignWare Core USB3 IP inside,
[all …]
/linux-6.15/Documentation/arch/arm/
H A Dmarvell.rst31 Core:
79 Core:
111 Core:
132 Core:
151 Core:
160 Core:
177 Core:
187 Core:
202 Core:
237 Core:
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/linux-6.15/rust/kernel/
H A Dplatform.rs65 let pdev = unsafe { &*pdev.cast::<Device<device::Core>>() }; in probe_callback()
167 fn probe(dev: &Device<device::Core>, id_info: Option<&Self::IdInfo>) in probe() argument
193 impl Deref for Device<device::Core> {
207 impl From<&Device<device::Core>> for ARef<Device> {
208 fn from(dev: &Device<device::Core>) -> Self { in from()
H A Dpci.rs69 let pdev = unsafe { &*pdev.cast::<Device<device::Core>>() }; in probe_callback()
240 fn probe(dev: &Device<device::Core>, id_info: &Self::IdInfo) -> Result<Pin<KBox<Self>>>; in probe() argument
411 impl Device<device::Core> {
425 impl Deref for Device<device::Core> {
439 impl From<&Device<device::Core>> for ARef<Device> {
440 fn from(dev: &Device<device::Core>) -> Self { in from()
H A Ddevice.rs226 pub struct Core; struct
231 impl Sealed for super::Core {} implementation
235 impl DeviceContext for Core {} implementation
/linux-6.15/Documentation/devicetree/bindings/media/
H A Dmediatek,vcodec-subdev-decoder.yaml21 | input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer |
24 LAT Workqueue | Core Workqueue <parent>
35 pipeline, such as LAT-SoC, LAT and Core.
49 2. Core Workqueue, for Core decoder:
52 after the Core decoding is done.
67 MT8195: LAT-SoC + LAT + Core
68 MT8192: LAT + Core
69 MT8188: LAT + Core
70 MT8186: Core
/linux-6.15/Documentation/networking/caif/
H A Dlinux_caif.rst32 * CAIF Core Protocol Implementation
47 ! +------+ <- CAIF Core Protocol
49 ! ! Core !
63 CAIF Core Protocol Layer
66 CAIF Core layer implements the CAIF protocol as defined by ST-Ericsson.
75 The Core CAIF implementation contains:
180 CAIF Core protocol. The IP Interface and CAIF socket have an instance of
181 'struct cflayer', just like the CAIF Core protocol stack.
/linux-6.15/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,apr-services.yaml22 3 = DSP Core Service
29 10 = Core voice stream.
30 11 = Core voice processor.
/linux-6.15/Documentation/devicetree/bindings/display/ti/
H A Dti,omap-dss.txt11 The OMAP Display Subsystem (DSS) hardware consists of DSS Core, DISPC module and
12 a number of encoder modules. All DSS versions contain DSS Core and DISPC, but
15 The DSS Core is the parent of the other DSS modules, and manages clock routing,
27 The DSS Core and the encoders have video port outputs. The structure of the
90 DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
/linux-6.15/drivers/gpu/nova-core/
H A DKconfig2 tristate "Nova Core GPU driver"
8 Choose this if you want to build the Nova Core driver for Nvidia
H A Ddriver.rs3 use kernel::{bindings, c_str, device::Core, pci, prelude::*};
30 fn probe(pdev: &pci::Device<Core>, _info: &Self::IdInfo) -> Result<Pin<KBox<Self>>> { in probe() argument
/linux-6.15/Documentation/devicetree/bindings/watchdog/
H A Dstarfive,jh7100-wdt.yaml42 - description: Core clock
73 - description: Core reset
79 - description: Core reset
/linux-6.15/samples/rust/
H A Drust_driver_platform.rs5 use kernel::{c_str, device::Core, of, platform, prelude::*, types::ARef};
25 pdev: &platform::Device<Core>, in probe() argument
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-bus-platform-devices-ampere-smpro39 …| CPM (core) | 0 | 2 | Armv8 Core 1 | CPM # …
154 …| Core's CE | /sys/bus/platform/devices/smpro-errmon.*/error_core_ce | Core has CE error …
156 …| Core's UE | /sys/bus/platform/devices/smpro-errmon.*/error_core_ue | Core has UE error …
192 …| Core's CE | /sys/bus/platform/devices/smpro-errmon.*/overflow_core_ce | Core CE error overflow…
194 …| Core's UE | /sys/bus/platform/devices/smpro-errmon.*/overflow_core_ue | Core UE error overflow…
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dmvebu-corediv-clock.txt1 * Core Divider Clock bindings for Marvell MVEBU SoCs
12 - reg : must be the register address of Core Divider control register
/linux-6.15/Documentation/devicetree/bindings/soc/nuvoton/
H A Dnuvoton,gfxi.yaml7 title: Graphics Core Information block in Nuvoton SoCs
14 The Graphics Core Information (GFXI) are a block of registers in Nuvoton SoCs
/linux-6.15/arch/arm64/boot/dts/apple/
H A Ds5l8960x-pmgr.dtsi15 apple,always-on; /* Core device */
24 apple,always-on; /* Core device */
51 apple,always-on; /* Core device */
60 apple,always-on; /* Core device */
69 apple,always-on; /* Core device */
78 apple,always-on; /* Core device */
404 apple,always-on; /* Core device */
456 apple,always-on; /* Core device */
465 apple,always-on; /* Core device */
474 apple,always-on; /* Core device */
[all …]
H A Dt7001-pmgr.dtsi15 apple,always-on; /* Core device */
24 apple,always-on; /* Core device */
33 apple,always-on; /* Core device */
42 apple,always-on; /* Core device */
59 apple,always-on; /* Core device */
68 apple,always-on; /* Core device */
77 apple,always-on; /* Core device */
327 apple,always-on; /* Core device */
499 apple,always-on; /* Core device */
508 apple,always-on; /* Core device */
[all …]
/linux-6.15/Documentation/devicetree/bindings/arm/stm32/
H A Dstm32.yaml146 - description: Engicam i.Core STM32MP1 SoM based Boards
149 - engicam,icore-stm32mp1-ctouch2 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0
150 … - engicam,icore-stm32mp1-ctouch2-of10 # STM32MP1 Engicam i.Core STM32MP1 C.TOUCH 2.0 10.1" OF
151 … - engicam,icore-stm32mp1-edimm2.2 # STM32MP1 Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit
152 - const: engicam,icore-stm32mp1 # STM32MP1 Engicam i.Core STM32MP1 SoM
/linux-6.15/sound/pcmcia/
H A DKconfig25 tristate "Sound Core PDAudioCF"
28 Say Y here to include support for Sound Core PDAudioCF

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