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Searched refs:CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2890 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x000003ffL macro
H A Dgfx_7_2_sh_mask.h3177 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff macro
H A Dgfx_8_0_sh_mask.h3791 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff macro
H A Dgfx_8_1_sh_mask.h4313 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1288 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_9_1_sh_mask.h1187 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_9_2_1_sh_mask.h1154 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_9_4_3_sh_mask.h1204 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_9_4_2_sh_mask.h1787 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_11_5_0_sh_mask.h3784 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_11_0_0_sh_mask.h6631 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_12_0_0_sh_mask.h7072 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_10_1_0_sh_mask.h6772 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_11_0_3_sh_mask.h7406 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro
H A Dgc_10_3_0_sh_mask.h7038 #define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK … macro