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Searched refs:CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c2937 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_init_gfx_power_gating()
5042 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_update_3d_clock_gating()
5092 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_0_update_coarse_grain_clock_gating()
H A Dgfx_v7_0.c3825 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v7_0_init_gfx_cgpg()
H A Dgfx_v9_4_3.c2651 (0x3345 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
H A Dgfx_v10_0.c8003 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v10_0_update_3d_clock_gating()
8063 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v10_0_update_coarse_grain_clock_gating()
H A Dgfx_v12_0.c3938 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v12_0_update_coarse_grain_clock_gating()
H A Dgfx_v11_0.c5294 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); in gfx_v11_0_update_coarse_grain_clock_gating()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2847 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x00000010 macro
H A Dgfx_7_2_sh_mask.h3082 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro
H A Dgfx_8_0_sh_mask.h3696 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro
H A Dgfx_8_1_sh_mask.h4218 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1218 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_9_1_sh_mask.h1117 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h1084 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h1134 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h1717 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h3723 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h6570 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h7011 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h6706 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h7345 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h6972 #define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT … macro