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Searched refs:CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1861 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2 macro
H A Dgfx_8_1_sh_mask.h2383 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11200 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_9_1_sh_mask.h12677 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_9_2_1_sh_mask.h12475 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_9_4_3_sh_mask.h14295 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_9_4_2_sh_mask.h2584 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_11_5_0_sh_mask.h12350 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_11_0_0_sh_mask.h15612 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_12_0_0_sh_mask.h11994 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_10_1_0_sh_mask.h18159 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_11_0_3_sh_mask.h17767 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro
H A Dgc_10_3_0_sh_mask.h16510 #define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK … macro