Home
last modified time | relevance | path

Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1878 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 macro
H A Dgfx_8_1_sh_mask.h2400 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11198 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_9_1_sh_mask.h12675 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h12473 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h14293 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h2582 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h12344 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h15606 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h11988 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h18153 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h17761 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h16504 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT … macro