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Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1871 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000 macro
H A Dgfx_8_1_sh_mask.h2393 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11205 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_9_1_sh_mask.h12682 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_9_2_1_sh_mask.h12480 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_9_4_3_sh_mask.h14300 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_9_4_2_sh_mask.h2589 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_11_5_0_sh_mask.h12355 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_11_0_0_sh_mask.h15617 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_12_0_0_sh_mask.h11999 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_10_1_0_sh_mask.h18164 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_11_0_3_sh_mask.h17772 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro
H A Dgc_10_3_0_sh_mask.h16515 #define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK … macro