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Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1866 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 macro
H A Dgfx_8_1_sh_mask.h2388 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11192 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_9_1_sh_mask.h12669 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h12467 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h14287 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h2576 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h12338 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h15600 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h11982 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h18147 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h17755 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h16498 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT … macro