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Searched refs:CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h1864 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 macro
H A Dgfx_8_1_sh_mask.h2386 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11191 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_9_1_sh_mask.h12668 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h12466 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h14286 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h2575 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h12337 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h15599 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h11981 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h18146 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h17754 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h16497 #define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT … macro