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Searched refs:CP_MQD_CONTROL (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1119 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_mqd_init()
1210 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v11_0_queue_init_register()
H A Dmes_v12_0.c1203 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in mes_v12_0_mqd_init()
1301 data = REG_SET_FIELD(data, CP_MQD_CONTROL, VMID, 0); in mes_v12_0_queue_init_register()
H A Dgfx_v9_4_3.c1845 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v9_4_3_xcc_mqd_init()
H A Dgfx_v12_0.c3076 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v12_0_compute_mqd_init()
H A Dgfx_v8_0.c4464 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v8_0_mqd_init()
H A Dgfx_v11_0.c4189 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v11_0_compute_mqd_init()
H A Dgfx_v9_0.c3590 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v9_0_mqd_init()
H A Dgfx_v10_0.c6925 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); in gfx_v10_0_compute_mqd_init()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dcikd.h1542 #define CP_MQD_CONTROL 0xC99C macro
H A Dcik.c4646 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL); in cik_cp_compute_resume()
4648 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); in cik_cp_compute_resume()