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Searched refs:CP_ME_CNTL (Results 1 – 16 of 16) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2609 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2612 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2618 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2621 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_pfp_cache_rs64()
2732 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2735 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2741 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
2744 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_config_me_cache_rs64()
3220 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
3223 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v11_0_cp_gfx_load_pfp_microcode_rs64()
[all …]
H A Dgfx_v12_0.c2077 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2078 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1); in gfx_v12_0_config_gfx_rs64()
2082 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0); in gfx_v12_0_config_gfx_rs64()
2135 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
2138 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
2144 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
2147 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_pfp_ucode_start_addr()
2177 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_me_ucode_start_addr()
2180 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_me_ucode_start_addr()
2186 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, in gfx_v12_0_set_me_ucode_start_addr()
[all …]
H A Dgfx_v9_0.c3221 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3223 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3224 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3225 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3226 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3227 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3228 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3229 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3230 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
3231 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v9_0_cp_gfx_enable()
[all …]
H A Dgfx_v8_0.c4111 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4112 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4113 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); in gfx_v8_0_cp_gfx_enable()
4115 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4116 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); in gfx_v8_0_cp_gfx_enable()
4117 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); in gfx_v8_0_cp_gfx_enable()
H A Dsid.h970 #define CP_ME_CNTL 0x21B6 macro
H A Dgfx_v10_0.c6039 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
6040 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
6041 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); in gfx_v10_0_cp_gfx_enable()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dni.c1438 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1442 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1820 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
H A Drv770d.h335 #define CP_ME_CNTL 0x86D8 macro
H A Dnid.h318 #define CP_ME_CNTL 0x86D8 macro
H A Dsid.h1027 #define CP_ME_CNTL 0x86D8 macro
H A Dcikd.h1108 #define CP_ME_CNTL 0x86D8 macro
H A Dsi.c3443 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3447 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3860 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
4029 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
H A Drv770.c1084 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
H A Devergreen.c3017 WREG32(CP_ME_CNTL, cp_me); in evergreen_cp_start()
3908 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_soft_reset()
4018 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_pci_config_reset()
H A Devergreend.h461 #define CP_ME_CNTL 0x86D8 macro
H A Dcik.c3866 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
3870 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
4947 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
5151 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()