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Searched refs:CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c2583 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2609 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2610 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v9_4_3_xcc_update_medium_grain_clock_gating()
2768 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v9_4_3_get_clockgating_state()
H A Dgfx_v6_0.c2592 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v6_0_enable_mgcg()
2616 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v6_0_enable_mgcg()
2617 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v6_0_enable_mgcg()
H A Dgfx_v7_0.c3538 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v7_0_enable_mgcg()
3591 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v7_0_enable_mgcg()
3592 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v7_0_enable_mgcg()
H A Dgfx_v9_0.c4970 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
4999 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v9_0_update_medium_grain_clock_gating()
5000 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v9_0_update_medium_grain_clock_gating()
5306 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v9_0_get_clockgating_state()
H A Dgfx_v8_0.c5458 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v8_0_get_clockgating_state()
5677 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v8_0_update_medium_grain_clock_gating()
5678 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v8_0_update_medium_grain_clock_gating()
H A Dgfx_v10_0.c7930 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v10_0_update_medium_grain_clock_gating()
7949 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { in gfx_v10_0_update_medium_grain_clock_gating()
7950 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; in gfx_v10_0_update_medium_grain_clock_gating()
8493 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) in gfx_v10_0_get_clockgating_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2598 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x00000001L macro
H A Dgfx_7_2_sh_mask.h1435 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
H A Dgfx_8_0_sh_mask.h1879 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
H A Dgfx_8_1_sh_mask.h2401 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11217 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
H A Dgc_9_1_sh_mask.h12694 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
H A Dgc_9_2_1_sh_mask.h12492 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
H A Dgc_9_4_3_sh_mask.h14312 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
H A Dgc_9_4_2_sh_mask.h2601 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
H A Dgc_10_1_0_sh_mask.h18180 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro
H A Dgc_10_3_0_sh_mask.h16531 #define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK … macro