Home
last modified time | relevance | path

Searched refs:CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c1694 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | in gfx_v9_4_3_xcc_cp_compute_enable()
H A Dgfx_v9_0.c3444 CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | in gfx_v9_0_cp_compute_enable()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h2763 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000 macro
H A Dgfx_8_1_sh_mask.h3285 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h844 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_9_1_sh_mask.h743 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_9_2_1_sh_mask.h732 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_9_4_3_sh_mask.h782 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_9_4_2_sh_mask.h1365 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_11_5_0_sh_mask.h20032 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_11_0_0_sh_mask.h23993 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_10_1_0_sh_mask.h6320 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_11_0_3_sh_mask.h26339 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro
H A Dgc_10_3_0_sh_mask.h6893 #define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK … macro