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Searched refs:CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c1690 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | in gfx_v9_4_3_xcc_cp_compute_enable()
H A Dgfx_v9_0.c3440 CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | in gfx_v9_0_cp_compute_enable()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h2755 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000 macro
H A Dgfx_8_1_sh_mask.h3277 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h840 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_9_1_sh_mask.h739 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_9_2_1_sh_mask.h728 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_9_4_3_sh_mask.h778 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_9_4_2_sh_mask.h1361 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_11_5_0_sh_mask.h20028 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_11_0_0_sh_mask.h23989 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_12_0_0_sh_mask.h13847 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_10_1_0_sh_mask.h6316 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_11_0_3_sh_mask.h26335 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro
H A Dgc_10_3_0_sh_mask.h6889 #define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK … macro