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Searched refs:CP_MEC_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu8_smumgr.c193 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); in smu8_load_mec_firmware()
194 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); in smu8_load_mec_firmware()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dcikd.h1094 #define CP_MEC_CNTL 0x8234 macro
1098 #define CP_MEC_CNTL 0x8234 macro
H A Dcik.c4220 WREG32(CP_MEC_CNTL, 0); in cik_cp_compute_enable()
4231 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); in cik_cp_compute_enable()
4950 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_soft_reset()
5154 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_pci_config_reset()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3478 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3482 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3486 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3490 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3498 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3501 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
H A Damdgpu_amdkfd_gfx_v9.c1208 pipe_reset_data = REG_SET_FIELD(pipe_reset_data, CP_MEC_CNTL, MEC_ME1_PIPE0_RESET, 1); in kgd_gfx_v9_hqd_reset()
H A Dgfx_v11_0.c3762 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); in gfx_v11_0_cp_compute_enable()
3764 data = REG_SET_FIELD(data, CP_MEC_CNTL, in gfx_v11_0_cp_compute_enable()
3767 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); in gfx_v11_0_cp_compute_enable()
3768 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); in gfx_v11_0_cp_compute_enable()