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Searched refs:CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h1588 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f macro
H A Dgfx_8_0_sh_mask.h2038 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f macro
H A Dgfx_8_1_sh_mask.h2560 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11366 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_9_1_sh_mask.h12842 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h12627 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h14571 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h2762 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h12542 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h15848 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h18331 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h18039 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h16679 #define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT … macro