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Searched refs:CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h1543 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 macro
H A Dgfx_8_0_sh_mask.h1985 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 macro
H A Dgfx_8_1_sh_mask.h2507 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11323 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12799 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12584 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14528 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2719 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12499 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15805 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h12214 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h18288 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17996 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16636 #define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK … macro