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Searched refs:CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2360 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L macro
H A Dgfx_7_2_sh_mask.h1163 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 macro
H A Dgfx_8_0_sh_mask.h1485 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 macro
H A Dgfx_8_1_sh_mask.h2009 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10782 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12259 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12063 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h13790 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2079 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12020 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15204 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h11688 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17698 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17359 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h15958 #define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK … macro