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Searched refs:CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2356 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L macro
H A Dgfx_7_2_sh_mask.h1155 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Dgfx_8_0_sh_mask.h1477 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Dgfx_8_1_sh_mask.h2001 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h10778 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12255 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12059 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h13786 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2075 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12016 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15200 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h11684 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17694 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17355 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h15954 #define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK … macro