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Searched refs:CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2401 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x00000016 macro
H A Dgfx_7_2_sh_mask.h1204 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 macro
H A Dgfx_8_0_sh_mask.h1538 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 macro
H A Dgfx_8_1_sh_mask.h2062 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11026 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_9_1_sh_mask.h12503 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h12307 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h14034 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h2323 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h12247 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h15431 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h17968 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h17586 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h16232 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT … macro