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Searched refs:CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2400 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L macro
H A Dgfx_7_2_sh_mask.h1203 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Dgfx_8_0_sh_mask.h1537 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
H A Dgfx_8_1_sh_mask.h2061 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11042 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12519 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12323 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14050 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2339 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12258 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15442 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17985 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17597 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16249 #define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK … macro