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Searched refs:CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11036 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12513 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12317 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14044 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2333 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12256 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15440 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17979 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17595 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16243 #define CP_INT_CNTL_RING1__GPF_INT_ENABLE_MASK … macro