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Searched refs:CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2396 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000L macro
H A Dgfx_7_2_sh_mask.h1213 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 macro
H A Dgfx_8_0_sh_mask.h1547 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 macro
H A Dgfx_8_1_sh_mask.h2071 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11047 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12524 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12328 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14055 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2344 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12263 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15447 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17990 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17602 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16254 #define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK … macro