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Searched refs:CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h2370 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L macro
H A Dgfx_7_2_sh_mask.h1191 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 macro
H A Dgfx_8_0_sh_mask.h1519 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 macro
H A Dgfx_8_1_sh_mask.h2043 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11015 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h12492 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h12296 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h14023 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h2312 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h12241 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h15425 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h11861 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h17956 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h17580 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h16220 #define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK … macro