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Searched refs:CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT (Results 1 – 18 of 18) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v12.c231 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | in update_mqd()
H A Dkfd_mqd_manager_v10.c215 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | in update_mqd()
H A Dkfd_mqd_manager_vi.c226 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; in __update_mqd()
H A Dkfd_mqd_manager_v11.c268 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | in update_mqd()
H A Dkfd_mqd_manager_v9.c298 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT | in update_mqd()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h3968 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 macro
H A Dgfx_8_1_sh_mask.h4490 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12901 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_9_1_sh_mask.h14201 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h14066 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h16432 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h3998 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h14067 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h17373 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h13273 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h20308 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h19612 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h18462 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT … macro