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Searched refs:CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h3967 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 macro
H A Dgfx_8_1_sh_mask.h4489 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12918 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_9_1_sh_mask.h14218 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_9_2_1_sh_mask.h14083 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_9_4_3_sh_mask.h16450 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_9_4_2_sh_mask.h4016 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_11_5_0_sh_mask.h14084 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_11_0_0_sh_mask.h17390 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_12_0_0_sh_mask.h13289 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_10_1_0_sh_mask.h20325 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_11_0_3_sh_mask.h19629 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro
H A Dgc_10_3_0_sh_mask.h18478 #define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK … macro