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Searched refs:CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h4117 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000 macro
H A Dgfx_8_1_sh_mask.h4639 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h13099 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_9_1_sh_mask.h14399 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_9_2_1_sh_mask.h14264 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_9_4_3_sh_mask.h16633 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_9_4_2_sh_mask.h4197 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_11_5_0_sh_mask.h14336 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_11_0_0_sh_mask.h17642 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_10_1_0_sh_mask.h20522 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_11_0_3_sh_mask.h19887 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro
H A Dgc_10_3_0_sh_mask.h18675 #define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK … macro