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Searched refs:CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h3252 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h3872 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h4394 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12757 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_9_1_sh_mask.h14057 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h13922 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h16285 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h3853 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h20786 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h24746 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h14213 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h20158 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h27185 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h18313 #define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT … macro