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Searched refs:CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2682 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd macro
H A Dgfx_8_0_sh_mask.h3254 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd macro
H A Dgfx_8_1_sh_mask.h3776 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19428 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_9_1_sh_mask.h20735 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h20662 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h22792 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h12889 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h22834 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h26822 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h14652 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h27341 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h29322 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h25602 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT … macro