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Searched refs:CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2681 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x6000 macro
H A Dgfx_8_0_sh_mask.h3253 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 macro
H A Dgfx_8_1_sh_mask.h3775 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h19433 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_9_1_sh_mask.h20740 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_9_2_1_sh_mask.h20667 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_9_4_3_sh_mask.h22797 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_9_4_2_sh_mask.h12894 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_11_5_0_sh_mask.h22843 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_11_0_0_sh_mask.h26831 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_12_0_0_sh_mask.h14659 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_10_1_0_sh_mask.h27348 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_11_0_3_sh_mask.h29331 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro
H A Dgc_10_3_0_sh_mask.h25609 #define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK … macro