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Searched refs:CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h2506 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 macro
H A Dgfx_8_1_sh_mask.h3028 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h11947 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_9_1_sh_mask.h13373 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h13151 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h15158 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h3349 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h29555 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h33927 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h19541 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h39576 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h37012 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h36239 #define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT … macro