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Searched refs:CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h2024 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 macro
H A Dgfx_8_0_sh_mask.h2556 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 macro
H A Dgfx_8_1_sh_mask.h3078 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h615 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_9_1_sh_mask.h514 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h503 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h544 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h1133 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h3146 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h5990 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h6429 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h6049 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h6765 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h6302 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT … macro