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Searched refs:CPU_CTRL (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/drivers/accel/ivpu/
H A Divpu_hw_ip.c170 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in top_noc_qrenqn_check_37xx()
181 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in top_noc_qrenqn_check_40xx()
543 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
546 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
558 val = REG_SET_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_37xx()
561 val = REG_CLR_FLD(VPU_37XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_37xx()
585 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || in top_noc_qacceptn_check_37xx()
596 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QACCEPTN, CPU_CTRL, exp_val, val) || in top_noc_qacceptn_check_40xx()
615 if (!REG_TEST_FLD_NUM(VPU_37XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || in top_noc_qdeny_check_37xx()
626 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QDENY, CPU_CTRL, exp_val, val) || in top_noc_qdeny_check_40xx()
/linux-6.15/arch/arm/mach-orion5x/
H A Dbridge-regs.h11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104) macro