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Searched refs:CLK_TOP_UNIVPLL_D4 (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/include/dt-bindings/clock/
H A Dmt8516-clk.h52 #define CLK_TOP_UNIVPLL_D4 20 macro
H A Dmt8192-clk.h99 #define CLK_TOP_UNIVPLL_D4 87 macro
H A Dmediatek,mt8188-clk.h123 #define CLK_TOP_UNIVPLL_D4 112 macro
H A Dmt8195-clk.h156 #define CLK_TOP_UNIVPLL_D4 144 macro
/linux-6.15/drivers/clk/mediatek/
H A Dclk-mt8516.c47 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
H A Dclk-mt8167.c50 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
H A Dclk-mt8188-topckgen.c47 FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
H A Dclk-mt8192.c45 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
H A Dclk-mt8195-topckgen.c58 FACTOR_FLAGS(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4, 0),
/linux-6.15/arch/arm64/boot/dts/mediatek/
H A Dmt8195.dtsi2853 <&topckgen CLK_TOP_UNIVPLL_D4>;
2856 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2873 <&topckgen CLK_TOP_UNIVPLL_D4>;
2876 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2897 <&topckgen CLK_TOP_UNIVPLL_D4>;
2900 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
3007 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
H A Dmt8192.dtsi1828 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
H A Dmt8188.dtsi2502 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;