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Searched refs:CLK_SET_RATE_PARENT (Results 1 – 25 of 437) sorted by relevance

12345678910>>...18

/linux-6.15/drivers/clk/hisilicon/
H A Dclk-hi3670.c81 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x0, 3, 0, },
85 CLK_SET_RATE_PARENT, 0x0, 27, 0, },
103 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
105 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
107 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
109 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
111 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
165 CLK_SET_RATE_PARENT, 0x0, 5, 0, },
269 CLK_SET_RATE_PARENT, 0, 1, 0, },
[all …]
H A Dclk-hi3660.c53 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
55 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
57 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
59 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
61 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
63 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
65 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
67 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
69 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
71 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
[all …]
H A Dclk-hi6220.c167 { HI6220_CLK_BUS, "clk_bus", "clk_300m", CLK_SET_RATE_PARENT, 0x490, 0, 4, 7, },
168 { HI6220_MMC0_DIV, "mmc0_div", "mmc0_syspll", CLK_SET_RATE_PARENT, 0x494, 0, 6, 7, },
169 { HI6220_MMC1_DIV, "mmc1_div", "mmc1_syspll", CLK_SET_RATE_PARENT, 0x498, 0, 6, 7, },
170 { HI6220_MMC2_DIV, "mmc2_div", "mmc2_syspll", CLK_SET_RATE_PARENT, 0x49c, 0, 6, 7, },
171 { HI6220_HIFI_DIV, "hifi_div", "hifi_sel", CLK_SET_RATE_PARENT, 0x4a0, 0, 4, 7, },
172 { HI6220_BBPPLL0_DIV, "bbppll0_div", "bbppll_sel", CLK_SET_RATE_PARENT, 0x4a0, 8, 6, 15,},
173 { HI6220_CS_DAPB, "cs_dapb", "picophy_src", CLK_SET_RATE_PARENT, 0x4a0, 24, 2, 31,},
174 { HI6220_CS_ATB_DIV, "cs_atb_div", "cs_atb_syspll", CLK_SET_RATE_PARENT, 0x4a4, 0, 4, 7, },
264 { HI6220_DDRC_SRC, "ddrc_src", "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a8, 0, 4, 0, },
265 { HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src", CLK_SET_RATE_PARENT, 0x5a8, 8, 2, 0, },
[all …]
H A Dclk-hi3620.c133 { HI3620_TIMERCLK01, "timerclk01", "timer_rclk01", CLK_SET_RATE_PARENT, 0x20, 0, 0, },
134 { HI3620_TIMER_RCLK01, "timer_rclk01", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 1, 0, },
135 { HI3620_TIMERCLK23, "timerclk23", "timer_rclk23", CLK_SET_RATE_PARENT, 0x20, 2, 0, },
136 { HI3620_TIMER_RCLK23, "timer_rclk23", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x20, 3, 0, },
137 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
138 { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
139 { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
140 { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
166 { HI3620_TIMERCLK45, "timerclk45", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 3, 0, },
167 { HI3620_TIMERCLK67, "timerclk67", "rclk_tcxo", CLK_SET_RATE_PARENT, 0x40, 4, 0, },
[all …]
H A Dcrg-hi3798cv200.c103 CLK_SET_RATE_PARENT, 0x68, 4, 0, },
106 CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
108 CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
166 CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
168 CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
170 CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
172 CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
174 CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
176 CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
179 CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
[all …]
H A Dclk-hi3559a.c187 CLK_SET_RATE_PARENT, 0x170, 1, 0,
191 CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
195 CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
199 CLK_SET_RATE_PARENT, 0x214, 28, 0,
203 CLK_SET_RATE_PARENT, 0x23c, 28, 0,
207 CLK_SET_RATE_PARENT, 0x198, 23, 0,
319 CLK_SET_RATE_PARENT, 0x16c, 6, 0,
323 CLK_SET_RATE_PARENT, 0x16c, 5, 0,
327 CLK_SET_RATE_PARENT, 0x16c, 9, 0,
331 CLK_SET_RATE_PARENT, 0x16c, 8, 0,
[all …]
H A Dclk-hix5hd2.c73 CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
78 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
80 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
85 CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
87 CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
94 CLK_SET_RATE_PARENT, 0x120, 0, 0, },
97 CLK_SET_RATE_PARENT, 0x178, 0, 0, },
102 CLK_SET_RATE_PARENT, 0x06c, 4, 0, },
106 CLK_SET_RATE_PARENT, 0x06c, 8, 0, },
110 CLK_SET_RATE_PARENT, 0x06c, 12, 0, },
[all …]
H A Dcrg-hi3516cv300.c70 CLK_SET_RATE_PARENT, 0xe4, 19, 1, 0, uart_mux_table, },
72 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
74 CLK_SET_RATE_PARENT, 0xc4, 4, 2, 0, mmc_mux_table, },
76 CLK_SET_RATE_PARENT, 0xc4, 12, 2, 0, mmc_mux_table, },
78 CLK_SET_RATE_PARENT, 0xc4, 20, 2, 0, mmc2_mux_table, },
80 CLK_SET_RATE_PARENT, 0xc8, 4, 2, 0, mmc_mux_table, },
82 CLK_SET_RATE_PARENT, 0x38, 2, 2, 0, pwm_mux_table, },
94 { HI3516CV300_SPI0_CLK, "clk_spi0", "100m", CLK_SET_RATE_PARENT,
96 { HI3516CV300_SPI1_CLK, "clk_spi1", "100m", CLK_SET_RATE_PARENT,
99 { HI3516CV300_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
[all …]
/linux-6.15/drivers/clk/samsung/
H A Dclk-exynos7870.c502 CLK_SET_RATE_PARENT, 0),
513 CLK_SET_RATE_PARENT, 0),
516 CLK_SET_RATE_PARENT, 0),
519 CLK_SET_RATE_PARENT, 0),
522 CLK_SET_RATE_PARENT, 0),
530 CLK_SET_RATE_PARENT, 0),
533 CLK_SET_RATE_PARENT, 0),
536 CLK_SET_RATE_PARENT, 0),
539 CLK_SET_RATE_PARENT, 0),
542 CLK_SET_RATE_PARENT, 0),
[all …]
/linux-6.15/drivers/clk/mmp/
H A Dclk-of-pxa168.c125 CLK_SET_RATE_PARENT, in pxa168_pll_init()
184 …{PXA168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x1, 0x1, 0x0, 0, &reset_l…
187 …{PXA168_CLK_PWM0, "pwm0_clk", "pwm0_mux", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &pwm0_…
188 …{PXA168_CLK_PWM1, "pwm1_clk", "pwm1_mux", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &pwm1_…
189 …{PXA168_CLK_PWM2, "pwm2_clk", "pwm2_mux", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &pwm2_…
190 …{PXA168_CLK_PWM3, "pwm3_clk", "pwm3_mux", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &pwm3_…
194 …{PXA168_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_…
195 …{PXA168_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_…
196 …{PXA168_CLK_SSP2, "ssp2_clk", "ssp2_mux", CLK_SET_RATE_PARENT, APBC_SSP2, 0x3, 0x3, 0x0, 0, &ssp2_…
244 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
[all …]
H A Dclk-of-mmp2.c201 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
208 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
213 CLK_SET_RATE_PARENT, in mmp2_main_clk_init()
341 CLK_SET_RATE_PARENT, APMU_GPU, 4, 2, 0, &gpu_lock},
343 CLK_SET_RATE_PARENT, APMU_GPU, 6, 2, 0, &gpu_lock},
345 CLK_SET_RATE_PARENT, APMU_GPU, 12, 2, 0, &gpu_lock},
403 CLK_SET_RATE_PARENT, in mmp2_axi_periph_clk_init()
409 CLK_SET_RATE_PARENT, in mmp2_axi_periph_clk_init()
416 CLK_SET_RATE_PARENT, in mmp2_axi_periph_clk_init()
441 CLK_SET_RATE_PARENT, in mmp2_axi_periph_clk_init()
[all …]
H A Dclk-of-pxa910.c105 CLK_SET_RATE_PARENT, in pxa910_pll_init()
142 …{PXA910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_l…
145 …{PXA910_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_…
146 …{PXA910_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_…
147 …{PXA910_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_…
148 …{PXA910_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_…
152 …{PXA910_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, APBC_SSP0, 0x3, 0x3, 0x0, 0, &ssp0_…
153 …{PXA910_CLK_SSP1, "ssp1_clk", "ssp1_mux", CLK_SET_RATE_PARENT, APBC_SSP1, 0x3, 0x3, 0x0, 0, &ssp1_…
203 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
207 {PXA910_CLK_DFC, "dfc_clk", "pll1_4", CLK_SET_RATE_PARENT, APMU_DFC, 0x19b, 0x19b, 0x0, 0, NULL},
[all …]
H A Dclk-of-pxa1928.c80 CLK_SET_RATE_PARENT, in pxa1928_pll_init()
108 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
109 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
110 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
114 …{PXA1928_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0,…
117 …{PXA1928_CLK_PWM0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0,…
118 …{PXA1928_CLK_PWM1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0,…
119 …{PXA1928_CLK_PWM2, "pwm2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM2 * 4, 0x3, 0x3, 0x0,…
120 …{PXA1928_CLK_PWM3, "pwm3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM3 * 4, 0x3, 0x3, 0x0,…
126 …{PXA1928_CLK_SSP0, "ssp0_clk", "ssp0_mux", CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 0x3, 0x3, 0x…
[all …]
H A Dclk-pxa1908-apbc.c47 {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 3, 0, 0, NULL},
48 {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 3, 0, 0, NULL},
49 {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 3, 0, 0, NULL},
50 {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 3, 0, 0, NULL},
54 …{PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM1, 0x6, 2, 0, 0, NU…
55 …{PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM2, 0x2, 2, 0, 0, NU…
56 …{PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM3, 0x6, 2, 0, 0, NU…
57 …{PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 3, 0, 0, &uart…
58 …{PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 3, 0, 0, &uart…
78 CLK_SET_RATE_PARENT, in pxa1908_apb_periph_clk_init()
[all …]
/linux-6.15/drivers/clk/rockchip/
H A Dclk-rk3308.c199 MUX(0, "clk_uart0_mux", mux_uart0_p, CLK_SET_RATE_PARENT,
203 MUX(0, "clk_uart1_mux", mux_uart1_p, CLK_SET_RATE_PARENT,
207 MUX(0, "clk_uart2_mux", mux_uart2_p, CLK_SET_RATE_PARENT,
211 MUX(0, "clk_uart3_mux", mux_uart3_p, CLK_SET_RATE_PARENT,
215 MUX(0, "clk_uart4_mux", mux_uart4_p, CLK_SET_RATE_PARENT,
219 MUX(0, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
227 MUX(0, "clk_pdm_mux", mux_pdm_p, CLK_SET_RATE_PARENT,
263 MUX(0, "clk_i2s0_2ch_mux", mux_i2s0_2ch_p, CLK_SET_RATE_PARENT,
267 MUX(0, "clk_i2s1_2ch_mux", mux_i2s1_2ch_p, CLK_SET_RATE_PARENT,
284 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
[all …]
/linux-6.15/drivers/clk/qcom/
H A Ddispcc-sm8450.c302 .flags = CLK_SET_RATE_PARENT,
322 .flags = CLK_SET_RATE_PARENT,
337 .flags = CLK_SET_RATE_PARENT,
352 .flags = CLK_SET_RATE_PARENT,
366 .flags = CLK_SET_RATE_PARENT,
381 .flags = CLK_SET_RATE_PARENT,
396 .flags = CLK_SET_RATE_PARENT,
411 .flags = CLK_SET_RATE_PARENT,
425 .flags = CLK_SET_RATE_PARENT,
440 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dcamcc-sa8775p.c100 .flags = CLK_SET_RATE_PARENT,
123 .flags = CLK_SET_RATE_PARENT,
200 .flags = CLK_SET_RATE_PARENT,
250 .flags = CLK_SET_RATE_PARENT,
300 .flags = CLK_SET_RATE_PARENT,
392 .flags = CLK_SET_RATE_PARENT,
412 .flags = CLK_SET_RATE_PARENT,
427 .flags = CLK_SET_RATE_PARENT,
442 .flags = CLK_SET_RATE_PARENT,
457 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Ddispcc-sm8550.c292 .flags = CLK_SET_RATE_PARENT,
312 .flags = CLK_SET_RATE_PARENT,
327 .flags = CLK_SET_RATE_PARENT,
342 .flags = CLK_SET_RATE_PARENT,
356 .flags = CLK_SET_RATE_PARENT,
371 .flags = CLK_SET_RATE_PARENT,
386 .flags = CLK_SET_RATE_PARENT,
401 .flags = CLK_SET_RATE_PARENT,
415 .flags = CLK_SET_RATE_PARENT,
430 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dcamcc-sm8250.c89 .flags = CLK_SET_RATE_PARENT,
112 .flags = CLK_SET_RATE_PARENT,
163 .flags = CLK_SET_RATE_PARENT,
214 .flags = CLK_SET_RATE_PARENT,
265 .flags = CLK_SET_RATE_PARENT,
316 .flags = CLK_SET_RATE_PARENT,
413 .flags = CLK_SET_RATE_PARENT,
435 .flags = CLK_SET_RATE_PARENT,
456 .flags = CLK_SET_RATE_PARENT,
471 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Ddispcc-sc8280xp.c434 .flags = CLK_SET_RATE_PARENT,
448 .flags = CLK_SET_RATE_PARENT,
462 .flags = CLK_SET_RATE_PARENT,
476 .flags = CLK_SET_RATE_PARENT,
518 .flags = CLK_SET_RATE_PARENT,
532 .flags = CLK_SET_RATE_PARENT,
546 .flags = CLK_SET_RATE_PARENT,
560 .flags = CLK_SET_RATE_PARENT,
574 .flags = CLK_SET_RATE_PARENT,
588 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Dcamcc-sm8650.c108 .flags = CLK_SET_RATE_PARENT,
131 .flags = CLK_SET_RATE_PARENT,
185 .flags = CLK_SET_RATE_PARENT,
266 .flags = CLK_SET_RATE_PARENT,
320 .flags = CLK_SET_RATE_PARENT,
374 .flags = CLK_SET_RATE_PARENT,
428 .flags = CLK_SET_RATE_PARENT,
482 .flags = CLK_SET_RATE_PARENT,
536 .flags = CLK_SET_RATE_PARENT,
590 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Ddispcc1-sa8775p.c231 .flags = CLK_SET_RATE_PARENT,
251 .flags = CLK_SET_RATE_PARENT,
266 .flags = CLK_SET_RATE_PARENT,
281 .flags = CLK_SET_RATE_PARENT,
296 .flags = CLK_SET_RATE_PARENT,
311 .flags = CLK_SET_RATE_PARENT,
326 .flags = CLK_SET_RATE_PARENT,
341 .flags = CLK_SET_RATE_PARENT,
356 .flags = CLK_SET_RATE_PARENT,
371 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Ddispcc0-sa8775p.c231 .flags = CLK_SET_RATE_PARENT,
251 .flags = CLK_SET_RATE_PARENT,
266 .flags = CLK_SET_RATE_PARENT,
281 .flags = CLK_SET_RATE_PARENT,
296 .flags = CLK_SET_RATE_PARENT,
311 .flags = CLK_SET_RATE_PARENT,
326 .flags = CLK_SET_RATE_PARENT,
341 .flags = CLK_SET_RATE_PARENT,
356 .flags = CLK_SET_RATE_PARENT,
371 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Ddispcc-x1e80100.c263 .flags = CLK_SET_RATE_PARENT,
283 .flags = CLK_SET_RATE_PARENT,
298 .flags = CLK_SET_RATE_PARENT,
313 .flags = CLK_SET_RATE_PARENT,
328 .flags = CLK_SET_RATE_PARENT,
343 .flags = CLK_SET_RATE_PARENT,
358 .flags = CLK_SET_RATE_PARENT,
373 .flags = CLK_SET_RATE_PARENT,
388 .flags = CLK_SET_RATE_PARENT,
403 .flags = CLK_SET_RATE_PARENT,
[all …]
H A Ddispcc-sm8750.c344 .flags = CLK_SET_RATE_PARENT,
359 .flags = CLK_SET_RATE_PARENT,
381 .flags = CLK_SET_RATE_PARENT,
396 .flags = CLK_SET_RATE_PARENT,
411 .flags = CLK_SET_RATE_PARENT,
426 .flags = CLK_SET_RATE_PARENT,
441 .flags = CLK_SET_RATE_PARENT,
456 .flags = CLK_SET_RATE_PARENT,
471 .flags = CLK_SET_RATE_PARENT,
486 .flags = CLK_SET_RATE_PARENT,
[all …]

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